JPS6037515B2 - small electronic calculator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a small electronic calculator equipped with a regression calculation function.

BACKGROUND ART Small electronic calculators equipped with a linear regression calculation function have been put into practical use.

To perform linear regression calculations with these calculators, the linear equation y=a+bx..."[1]
The data (x,,y,)(ne,
y2)......Input n of (xn, yn) by key operation, execute the specified calculation, calculate the number of data n, i≧・, and calculate the coefficient b and y-intercept a of the straight line. demand.

Furthermore, an estimated value of x and an estimated value of Y can also be obtained. However, in order to perform regression calculations such as logarithms, exponents, and exponents using the above-mentioned calculators, the following extremely troublesome key operations were required.

That is, to perform logarithmic regression calculation, the equation of the logarithmic curve y
=a+binx ““”(4
} is the straight line equation Y=A+BX
......(5) and the following (6)
} It is necessary to calculate and input the transformed data (X, Y) in advance as shown in the formula.

In addition, in the case of exponential regression calculation, the exponential curve equation y:a
e Mosquito...{7} above {
5}, input the data (X, Y) transformed as shown, and further transform the obtained results A and B as shown, and the obtained a and b become the y-intercept and coefficient to be sought. .

The same is true for power regression calculations, where the equation of the power curve y
=aXb... [Make 1 addition correspond to the above formula (■), input, and from the obtained A and B, a=e^ .・．． ．．・．． (12)b
It was necessary to find =B.

Additionally, there are conventional calculators that have regression calculation functions other than linear regression, but such calculators have special keys for exponential regression calculations, for example, and have disadvantages such as increasing the size of the calculator itself. was there.

This invention was made in view of the above circumstances, and allows regression calculations such as logarithms, exponentials, powers, etc. to be performed using the same operations as when performing linear regression calculations, without requiring complicated operations or special keys for various regression calculations. The purpose is to provide a small electronic calculator that can perform calculations.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a ROM in which various microinstructions for controlling the operation of this computer are stored, and the microinstructions stored in the address specified by the ROM address section 2 are output. The microinstructions output from this ROMI include a signal Su that specifies the row address of a register that stores operands in RAM3, which will be described later, a signal Fu that specifies a row address of a register that stores operands, and a signal Fu that specifies the row address of a register that stores operands.
A signal SL that specifies the column address of the register that stores the operand or the processing start column address when processing spans multiple columns; A signal that specifies the column address of the register that stores the operand or the processing end column address. FL, numerical code C. , an operation code 0p such as an addition instruction, a subtraction instruction, or a transfer instruction, and a next address signal Na that specifies the address of the microinstruction to be executed next to the currently executed microinstruction. Above next address signal N
A is supplied to the address register 4 and is subtracted by a signal e, which will be described later. The output of the address section register 4 is decoded by the ROM address section 2 and supplied to the ROMI as an address selection signal. Further, the operation code ○p is supplied to the operation decoder 5. This operation decoder 5 decodes the above operation code ○p,
It outputs control signals and command signals for executing various calculations of this computer, such as control signals OS, KE, ID, OF and subtraction command SB that control opening and closing of various gate circuits.
, judgment command JU, specified digit length mode signal M, display/key sampling signal OP, etc. are output. The above specified digit length mode signal M and display/key sampling signal OP are as follows:
Clock pulses ◇,, timing signals t,, ra, t periodically output from a timing signal generation circuit (not shown)
3 and each microphone. During the first cycle of the period in which the command is executed, the timing signals t, -t3 are supplied to the timing decoder 6 together with the start command ST which is "1" during the period in which the timing signals t, -t3 are output for one cycle. Incidentally, the relationship between the timing signals output from the timing signal generation circuit is shown in FIG. timing signal t,,t2
, t3 are sequentially and periodically output in synchronization with clock pulses J, , ◇2. and 1 of the timing signal t, ~t3
Timing signal every cycle? D (at =t3.) is output. The timing decoder 6 receives the above signals and outputs various timing signals ga-c, ta-tc, an issue/write control signal R/W, and a gate control signal CI. The logical relationship between the above timing signals is ◇a
=t3・middle.・〇P, 〇b=t2・〇P, Small.

:t3・○,. M and D = Ra・F. ta=M・ST+M・upper. tb=M・t, tc=MOST It is.

Thus, the row address designating signals Su and Fu' of the RAM3 outputted from the ROMI are respectively connected to the gate circuits ○.
and ○2 to the row address input terminal UA of the RAM3.

The gate circuit ◯ is directly supplied with the timing signal t, and the gate circuit G2 is directly supplied with the timing signal t. is supplied via the inverter 7 to control the opening and closing of the gate. Further, a column address or processing start column address designation signal S and a column address or processing end column address designation signal F of the RAM 3 are input to the column address input terminal LA of the RAM 3 via gate circuits ○3 and 04, respectively. The gate circuits ◯3 and G4 are gate-controlled by timing signals ta and tb output from the timing decoder 6, respectively. Further, the output from the gate circuit ○3 is supplied to the counter 8. This counter 8 performs a counting operation in accordance with the timing signal Jc, and increments the counter by one each time the timing signal ◇c is input. The output of the counter 8 is applied to the column address input terminal LA of the RAM 3 via the gate circuit ○5, and is also applied to one input terminal of the matching circuit 9. The other input device of the coincidence circuit 9 is supplied with the processing end column address designation signal F from ROMI. The coincidence circuit 9 also includes an operation decoder 5.
A specified digit length mode signal M outputted from the inverter 10 is applied via an inverter 0, and when the output of this inverter 10 is "1", the matching circuit 9 is operated. The coincidence output of the coincidence circuit 9 is applied to an AND circuit 11 and is also input to a flip-flop 13 via an OR circuit 12. Furthermore, the above-mentioned digit designation length mode signal M is applied to this flip-flop 13 via an OR circuit 12. This flip-flop 13 is a delay type flip-flop, which inputs an input signal in synchronization with the timing signal o (=t3, middle,) and receives the clock pulse? 2, and the output becomes the start command ST mentioned above. Further, the specified digit length mode signal M is applied to the AND circuit 14. A timing signal ◇D is input to the AND circuits 11 and 14, and each output is sent to the OR circuit 15.
The signal is sent to the address section register 4 via the address section register 4 as a subtraction signal e. On the other hand, the data in the area in RAM3 designated by the row address designation signal and column address designation signal from the ROMI is output as parallel 4-bit data from the output terminal OUT, and is gate-controlled by the timing signal etc. The signal is sent to the latch circuit 16 via the gate circuit G6, and is also sent to the latch circuit 17 via the gate circuit G7 whose gate is controlled by the timing signal J. The output of the latch circuit 16 is input to the column address input terminal LA of the RAM 3 via a gate circuit ○8 whose gate is controlled by a gate control signal m output from the operation decoder 5. Further, the output of the latch circuit 16 is supplied to the input terminal a of the arithmetic circuit 18 via a gate circuit 9 whose gate is controlled by a gate control signal OS output from the operation decoder 5. Further, the output from the latch circuit 17 is supplied to the input terminal b of the arithmetic circuit 18 via the gate circuit G, o which is gate-controlled by the gate control signal OF output from the operation decoder 5. sent to. Is this buffer 19 a timing signal?
It operates in synchronization with a and stores display data, and its output is sent to the display unit 21 via the decoder 20 and displayed. The calculation data from the calculation circuit 18 is supplied to the input terminal IN of the RAM 3 and is also applied to the AND circuit 23 via the OR circuit 22, and the carry or borrow from the calculation circuit 18 is sent to the AND circuit 24.
added to. The AND circuits 23 and 24 output a signal when the judgment instruction JU is given from the operation decoder 5, and the output signal is inputted to the address section register 4 as a next address change instruction. Further, data outputted from the latch circuit 16 via the gate circuit 9 is inputted to a buffer 25 which operates in synchronization with the timing signal b. This buffer 25 stores data for selecting digits of each display element of the display section 21, and this output is sent to the display section 21 as a digit signal via a decoder 26, and is also sent to the key input section 27 as a key sampling signal. Sent. The key input data output from the key input unit 27 is stored in 2M buffers operating in synchronization with the timing signal 0o, and gate circuits ○, . The signal is input to the input terminal a of the arithmetic circuit 18 via the input terminal a. Moreover, this input terminal a has R
Numeric code C output from OMI. However, the gate circuit○
, 2. This gate circuit G, 2 is gate-controlled by a signal CI output from a timing decoder 6. Next, the configuration of the RAM 3 will be explained with reference to FIG.

As mentioned above, this RAM 3 has a row address designation signal Su.
, Fu, are addressed by the column address designation signals SL and FL, and the issue/write control signal R/W is “0”.
”, the data in the specified area is read from the output terminal OUT, and when R/W is “1”, the data is written in the specified area from the input terminal IN, and the inside is 1.
It is made up of three registries. In order from the 0th line to the 12th line, the calculation display register AQ1, the first calculation auxiliary register Acc2, the second calculation auxiliary register Aq3,
In linear regression and/exponential regression, X=x is memorized, and in logarithmic regression and power Hata regression, x is initially memorized, and after a predetermined calculation, X=l
A register R1 for storing X data stores nx, a register R2 for storing Y data stores Y=y for linear and logarithmic regression, stores y initially for exponential and power regression, and stores Y=lny after a predetermined calculation; Register M1 for storing data number n, 2× storage register M2, ZX2 storage register M3, 2Y storage register M4, 2Y2 storage register M5, XXY storage register M6, Y-intercept A storage register AR, coefficient A B storage register BR is provided. A key sampling digit designation counter F is provided in the 19th line of the 0th line. In this embodiment, a 10-digit display is used, so the counter F, is 0 to 9.
count. Further, in the first IS line, there is provided a register F2 which becomes "1" when there is a key input. Furthermore, the 19th ring on the 5th row is a mode storage register C that stores the state of the mode changeover switch MS, which will be described later.
is provided. This mode storage register C is set to “2” when switch MS specifies linear regression calculation.
, "4" is stored when logarithmic regression calculation is specified, "8" is stored when exponential regression calculation is specified, and "12'' is stored when power regression calculation is specified.Next. The configuration of the main parts of the key input section 27 will be explained with reference to FIG. 4.The key input section 27 has modes for specifying linear, logarithmic, exponential, and power regression calculations as shown in FIG. Changeover switch MS, key X to input the x booter.
Key Yo for inputting y data, Key x for calculating the estimated value of x, Key y for calculating the estimated value for y, Key A for calculating the constant A.
K, a key BK for obtaining a constant B, other function keys FK such as 10, 1, ×, ÷, etc., and a numeric key NK, etc. are provided. The key input unit 27 and the decoder 26 that supplies the key sampling signal are configured as shown in FIG. 4, for example. That is, from the decoder 26, lines K, K
, , K2...Kn are sequentially output with sampling pulses. Then, the line averages are connected to the mode selection lines MOO1, MOD2, MOD3,
Connected to MOD4. This mode selection line MO
OI~MOD4 are arranged sequentially in the vertical direction together with lines K and ~Kn provided below this mode selection line, and key operation signal lines KE1 and Kn are arranged in the left and right direction.
E2, KE4, and KE8 are arranged in sequence, and each of the above lines forms a matrix connection. Lines K, ~Kn and lines KE, ~ in this matrix configuration
A key switch is arranged at each intersection of a matrix made up of KE8s. Furthermore, the key operation signal line KE
2 is connected to mode selection lines MOD1 and MOD4 by KE4.
is diode-connected to MOD2, and KE8 is diode-connected to MOD3 and MOD4, respectively. As shown in FIG. 5, the operations of the embodiment configured as described above include a key sampling operation shown in block S, a calendar number operation shown in block S2, a data input operation shown in block S3,
It consists of an operation for obtaining an estimated value of x shown in block S4, an operation for obtaining an estimated value for y shown in block S5, etc.

First, the key sampling operation will be explained with reference to the flowchart of FIG.

Block S, . At this time, the counter F of RAM3 is set to “0”.
" is set. The operation at this time is that the signal CI output from the timing decoder 6 becomes "1", the gate circuit G.2 opens, and the numerical code C. "0" is output from the ROMI.
is inputted to the input terminal IN' of the RAM 3 via the arithmetic circuit 18. On the other hand, when the timing signals become "1" (expressed as the following timings), the gate circuit 2 opens, and since the timing signal tb is also "1" at this time, the gate circuit G4 also opens. As a result, the row address designation signal Fu "0" and the column address designation signal F "15" are output from ROMI.
'' are applied to the row address input terminal UA and column address input terminal LA of the RAM 3, respectively, to designate the counter F,. Also, at this time, the read/write control signal R/W input to the RAM 3 becomes "1" (write command), so a numerical code "0" is written into the counter F. Next, in the flock S,2, the content of the counter F, is "9".
It is determined whether or not. In this case, the operation decoder 5 outputs the judgment instruction JU, the subtraction instruction SB, the gate control signal OF, and the specified digit length mode signal M, and the operation decoder 6 further outputs the gate control signal CI. At this timing, the row address designation signal Su and the column address designation signal SL are not output from the ROMI.
The RAM3 receives the signal R/W (0"), but no read operation is performed. On the other hand, since the signal CI is "1", the gate circuit 12 is opened, and the numerical code "9" is input from the ROMI to the arithmetic circuit 18. It is input to terminal a. At these timings, the gate circuits 02 and G4 open and the row address designation signal (hereinafter referred to as row address) Fu "0" and column address designation signal (hereinafter referred to as column address) FL "15" are sent from ROMI.
'' are input to the row address input terminal UA and column address input terminal LA of the RAM 3, respectively. Since the signal R/W is "0" at this time, the contents of the counter F are read out. This logic data is stored in the latch circuit 17 by opening the gate circuit G7 at the time when the timing signal EL becomes "1". At this time, the signal O
Since F is "1", the contents of the latch circuit 17 are input to the input terminal b of the arithmetic circuit 18. Since the arithmetic circuit 18 is given the subtraction instruction SB, the numerical code " 9” is subtracted. At timing t3, the data and borrow of the calculation result from the calculation circuit 18 are input to the address register 4 via the OR circuit 22 and AND circuits 23 and 24, respectively. At this time, the judgment instruction JU opens the AND circuits 23 and 24 at one input terminal of the AND circuits 23 and 24. When neither data nor borrow exists, the contents of the counter F, indicate that it is equal to "9", the address section register 4 outputs the next address signal Na as it is, and then the blocks S, . Enter. When the above data exists, it indicates that the contents of the counter F, are not equal to "9", the address section register 4 changes and outputs the next address signal Na, and the process moves to block S,3. Next, in the block S,3, the contents of the counter F, are transferred to the buffer 25, and the contents of the digit of Accl (Accl(
F,)) is transferred to the buffer 19. In this case, the gate control signals OS, OF, and ID output from the operation decoder 5 become "1". At a later timing, the contents of the counter F, are read out, and the output data is stored in the latch circuit 16 when the timing signal J becomes "1". At timing t2, the gate circuit G2 opens and the row address Fu'0 is transferred from the ROMI.
" is input to the row address input terminal UA of RAM3, and since the signal ID is "1", the gate circuit G8 is opened.
The contents of the latch circuit 16, that is, the contents of the counter F, are R
It is input to the column address input state LA of AM3. At this time, since the signal R/W input to RAM3 is "0", 1 (F,) of A is read out, and when the timing signal t2・J, becomes "1", the above The proposal data is stored in the latch circuit 17. On the other hand, the signal OS “
1", the gate circuit G9 is open, and at the time when b in the timing signal becomes "1", the latch circuit 16
The contents of are loaded into the buffer 25. This buffer 25
The contents of the counter F read in are supplied to the key input unit 27 as a key sampling signal by the key sampling decoder 26, and are supplied to the display unit 21 as a digit signal. On the other hand, it was read into buffer 9. The contents of 1(F,) of A are converted into segment signals by the display decoder 2 and supplied to the display section 21.
As a result, the contents of Acc1(F,) are displayed in the F digit of the display section 21. Next, in block S, 4, it is determined whether the content of counter F, is "ro". This judgment operation is similar to the block S,2 described above, and when the content of the counter F, is equal to "0", the block S,5
Proceed to. Also, when it is not equal to "0", the floating block S
, proceed to 7. In the block S,5, the state of the mode changeover switch MS is stored in the mode storage register C.
In other words, the contents of buffer 28 are written to mode storage register C in RAM3. In this case, the signal KE output from the operation decoder 5 becomes "1",
Gate circuit G, . opens. Timing signal. is “1”
At this point, the contents of the buffer 28, that is, the state of the mode switch
The input terminal IM of M3 is applied. Also, since gate circuits ○2 and G4 are open at this time, row address Fu "5" and column address FL "15" are input from ROMI to row address input terminal UA and column address input terminal LA of RAM3, respectively. At the same time, since the signal R/W input to RAM3 is "1", RAM3
The contents of the buffer 28, that is, the state of the mode switching switch MS ("2", "4", "
8” or “12”) is written. Next, Frock S
,6, 1 is added to the contents of the counter F,. In this case, the signals CI, OF, and M are "1", and the timing signal t
a is equal to t, and timing signal tb is equal to t. At timing t, the numerical code “1” is sent from ROMI.
'' is applied to the input terminal a of the arithmetic circuit 18, the contents of the counter F, are read out at the timing of
7, latch circuit 1 It is applied to input terminal b of the arithmetic circuit 18 via 7 and gate circuits G and o. At that timing, the contents of counter F, and the numerical code "1" are added, and the result of the operation is written to counter F. When the processing of block S, 6 is completed, blocks S,
At step 2, it is determined again whether the content of the counter F is "9" or not. On the other hand, if it is determined that the content of the counter F, in block S,4 is not "0", block S,7
In this case, the key operation data in the key input section 27 other than the mode changeover switch MS, that is, the contents of the buffer 28 is stored in the RAM.
3 is written to register F2. In this case, the signal KE output from the operation decoder 5 becomes "1", and the gate circuits G, . opens. Then, at the point in time when o in the timing signal becomes "1", the contents of the buffer 28 are written into the register F2 of the RMM 3 via the arithmetic circuit 18. Next, in block S,8, register F
By determining whether or not the content of 2 is "0", it is determined whether or not key input data exists. register F
If 2 is "0", the process returns to block S, 6; if it is not "0", the process proceeds to the next key change process. Next, the data input operation will be explained with reference to FIG.

When the x-data input key Xo is detected in block S, the process proceeds to block S2, where the contents of Accl, that is, the x-data, are transferred to the X-data storage register RI. In this case, the signal 06 is "1", the signal M is "0", and the timing signals ta=ST, tc=ST. Then, at timing t, the row address Su is set to ``0'' and the column address Fu is set to ``0''.
The content of the 0th digit of Accl is read out, and when the timing signal t,, low, becomes "1", the gate circuit G6
is opened, and the above-mentioned proposal data is stored in the latch circuit 16. At timing t2, gate circuit G2 opens and RO
Row address Fu "3" is input from MI to row address input terminal UA of RAM3. On the other hand, column address FL "14" is output from ROMI, but timing signal tb
Since is "0", the gate circuit ○4 is not opened, and no input is made to the column address input terminal LA of the RAM3. Instead, since the timing signal ta is "1", the gate circuit G3 is opened and the column address SL "0" is input to the column address input terminal LA of the RAM3. Therefore, the contents of the 0th digit of the X data storage register RI are read out, and the timing signal etc.
When J, becomes "1", the gate circuit G7 is opened and the read data is stored in the latch circuit 17. At this time, since the signal OF is "0", the contents of the latch circuit 17 are not applied to the input terminal b of the arithmetic circuit 18. On the other hand, since the signal OS is "1", the gate circuit G,. is open.
Therefore, the contents of the latch circuit 16, that is, the contents of the 0th digit of Accl, are supplied to the input terminal a of the arithmetic circuit 18. At timing t3, the contents of the 0th digit of Accl input to the arithmetic circuit 18 as described above are supplied to the input terminal IN of the RAM 3. At this time, the signal R/W is "1", and the row address Fu "3" and column address SL "0" are respectively sent from the ROMI to the row address input terminal UA and column address input terminal LA of the RAM3. Since the above A is the content of the 0th digit of 1, the content of the 0th digit of register RI is
written to the digit. Then, the timing signal ◇c is “1”
Then, the counter 8 counts up by one. At timing t of the next cycle, the gate circuit G,
is opened, and the row address Su “0” is transferred from ROMI to RAM3.
is supplied to the row address input terminal UA of. On the other hand, since the timing signal ta becomes "0", the gate circuit 03 is closed, and the timing signal tc becomes "1", so that the gate circuit G5
opens. Then, the content "1" of the counter 8 is input to the column address input terminal LA of the RAM 3. This allows Ac
The contents of the first digit of c1 are read and the timing signal t.・
At the time when the signal becomes "1", the gate circuit ○6 is opened and the above-mentioned proposal data is stored in the latch circuit 16. Next, at timing t2, the counter 8 is
The count value "1" is input to the column address input terminal LA of the RAM3. Then, at timing t3, the contents of the first digit of AccI are written to the first digit of register RI.
Also, timing signals? When c becomes "1", the counter 8 counts up by one and makes the count value "2". Thereafter, the count value of the counter 8 is increased every cycle (t, to t3), and the above operation is repeated. and,
The count value of counter 8 is ROMI column address FL "14"
'', the coincidence circuit 9 outputs a coincidence signal.
And timing signals. When (=ra・?,) becomes "1", the coincidence signal is applied to the address section register 4 via the AND circuit 11, so that the next address signal Na output from the ROMI is applied to this address section register. 4 and proceed to the next step. Next, in block S23, the contents of the mode storage register C are determined, and it is determined whether the mode changeover switch MS specifies linear regression calculation, logarithmic regression calculation, exponential regression calculation, or power regression calculation. be done. In this case, the operation decoder 5 outputs the judgment instruction JU and the subtraction instruction SB, and the signals CI, OF, and M are ``1''.Then, the contents of the mode storage register C are subtracted from the numerical code ``4''. As a result, when there is neither data nor borrow, the content of the mode storage register C is equal to "4", so it is determined that the mode switching switch MS is instructing logarithmic regression calculation. At this time, block S24
An operation is performed to obtain the natural logarithm of the contents of register RI. In addition, when the above data is output but not output, this means that the content of the mode storage register C is smaller than "4", and the mode switching switch MS instructs linear calculation. It is determined that the In response, the address section register 4 changes the next address signal Na, block S27 is executed, and an operation is performed using the data x, y as they are inputted by the key operation. Furthermore, if both data and borrow are output as the result of the above subtraction, it means that the content of the mode storage register C is greater than "4", and this causes the mode selector switch MS to switch to exponential or power regression calculation. is specified. In response, the address section register 4 changes the next address signal Na, and the process advances to block S25. In block S25, an operation is performed to obtain the natural logarithm of the contents of the Y data storage register R2. Then, in block S, it is determined whether the content of mode storage register C is "8" or not. When the content of the mode storage register C is equal to "8", it is determined that the mode changeover switch MS specifies exponential regression calculation. Therefore, next in block S27, the x data that is still being keyed and the natural logarithm of Y
An operation is performed using the data (lny). Also,
When the content of the mode storage register C is not equal to "8", it is determined that the mode changeover switch MS specifies the power-soft regression calculation. Therefore, next, in block S, the natural logarithm of the contents of register RI is determined. Next, in block S27, an operation is performed using the natural logarithmized data X, Y (lnx, lny>).Next, referring to FIG. explain.

First of all, bu. In the test S, the following calculations are performed.

Next, in block S32, the mode storage register C is set to "
4" is determined. If the content of the mode storage register C is equal to or less than 4, this means that the mode changeover switch MS specifies linear regression calculation or exponential regression calculation, so next block S At Matsu, A Qin of e is determined using A determined in block S3, and it is written to Accl. Then, when the AK key is operated, the information is displayed on the display section 21. This is the a that should be found. Regarding the constant b, the B obtained by can be used as b in any regression calculation, and is displayed by operating the BK key.

Next, the operation for determining the estimated value of y will be explained with reference to FIG. If you operate the Y key after inputting the data x, you will enter block S4, and the contents of mode storage register C will be "4".
” is determined. When the content of the mode storage register C is smaller than "4", it means that the mode changeover switch MS specifies linear regression calculation, so next in block S42, the content of Accl is directly stored in the register R. , will be forwarded to. Then, in block S45, the estimated value of Y is determined using the key-input x data as is. Furthermore, when the contents of the mode storage register C are equal to or greater than "4",
This means that the mode changeover switch MS specifies one of logarithmic, exponential, and power regression calculations. In this case, it is further determined in block S43 whether the content of the mode storage register C is equal to "8" or not. When the content of the mode storage register C is equal to "8", it means that the mode changeover switch MS is specifying exponential regression calculation, and in this case, B. At step S42, the contents of A-1 are transferred to register RI. Next, in block S45, the estimated value of Y is determined using the key-input x data as is. In addition, if it is determined that the content of the mode storage register C is not equal to "8J," it means that the mode changeover switch MS specifies logarithm or power regression calculation, and in this case, in block S44, A
The natural logarithm of the contents of ccl is determined and written to register RI. Then, in block S45', an estimated value of Y is obtained using x, which is obtained by taking the natural logarithm of the x data input by key operation. Next, in block S46, it is again determined whether the content of the mode storage register C is "4". If 4 is equal to 4, then it is a linear or logarithmic regression calculation, so 70xS
At step 47, the estimated value of Y stored in the register R2 is directly transferred to AQI and displayed as the estimated value y. If it is determined in block S46 that the content of the mode storage register C is greater than "4", the calculation is an exponential or power-mill regression calculation, so the above-mentioned check of the content of the register R2 is performed in block S48. Take the sponential, transfer the obtained e(R2) to 1 in A, and display it.
This becomes the estimated value y to be found. Next, the operation for determining the estimated value of x will be explained with reference to FIG.

If you operate the X key after inputting the data of y, the block S5,
Then, it is determined whether the contents of the mode storage register C are equal to "4". If it is equal to or smaller than "4", the process advances to block S52 and the contents of Acc1 are transferred as they are to register R2. If the content of the mode storage register C is greater than "4", the process proceeds to block S53, where the natural logarithm of the content of Accl is calculated and transferred to the register R2. Then, in block 4, an estimated value of X is obtained using the contents of register R2, and the obtained estimated value is stored in register RI. Next, the process advances to block S55, where it is determined whether the contents of the mode storage register C are equal to "4". If it is smaller than "4", the process advances to block S57 and the contents of register RI are transferred to Accl as they are; if it is equal to or larger than "4", the contents of mode storage register C are changed to "8" again in block S56. compare. If it is equal to "8", the process proceeds to block S57, and if it is determined to be greater than "8", the process proceeds to block S58, where the register RI
The exponential of the contents is taken and transferred to Accl. Then, the contents of this Accl are displayed, and this becomes the estimated value x to be obtained. Figure 11 shows data x,,y
,, indicates the memory contents of each register in RAM3 when 2, 3, 3, 4 are input as x2, y2, and when y = 5 is input and the key × to obtain the estimated value of x is operated. It is. In the figure, the columns labeled 2, 3 and 3, 4 data input indicate the contents of each register after inputting y data "3" and "4" and executing a predetermined operation, and 5 inputs for y. The column after pressing the X key shows the contents of each register after performing a predetermined operation after pressing the X key. In the above embodiment, linear, logarithmic, exponential, and power-hata regression calculations are performed, but the present invention can also be applied to other regression calculations.

In addition, in the above embodiment, the calculation procedure for linear regression calculation is stored in the storage device, and variable data for other regression calculations is transformed using this as a reference. However, this is not limited to this, and for example, logarithmic regression The calculation procedure may be stored in advance, and variable data for other regression calculations may be modified using this as a reference.

In addition, in the above embodiment, 2, 4, 8, and 12 are stored in the mode storage register C in correspondence with linear, logarithmic, exponential, and power regression calculations, but the values are limited to these values. isn't it.

Further, in the above embodiment, the mode storage register is RAM.
Although it is provided inside, it may be provided separately.

In addition, in the above embodiment, a RAM method is adopted, but
This can also be achieved by adopting a shift register method or the like.
Further, in the above embodiment, a slide switch is used as the regression mode setting means for setting the type of regression calculation, but the present invention is not limited to this, and a push-button rotor switch or the like may also be used.

Furthermore, instead of selecting the regression mode by selecting a key matrix, for example, a key counter and a counter are provided, and the state of this counter is changed every time a key is operated.
A regression mode may also be set. As is clear from the above description, the present invention automatically transforms data input from an input device such as a keyboard within a computer according to the type of regression calculation specified by the regression mode setting means. Since this deformed data is used to execute a pre-stored regression calculation means (for example, linear regression calculation) to perform the desired regression calculation, there is no need to perform troublesome calculation operations before data input as in the past. There is no need for the extremely troublesome key operation work of performing calculations from the output data and obtaining the desired results, just by switching the mode selector switch, using the same keys as for the predetermined regression calculation, and performing the same calculations. By operation, it is possible to perform various regression calculations, and it is possible to provide a highly reliable calculator that is extremely simple in terms of key operations. In addition, special keys for various regression calculations,
Since it is not equipped with a special microprogram, it has various advantages such as being able to downsize the computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of a small electronic calculator according to the present invention, FIG. 2 is a time chart showing the state of timing signals used in the above embodiment, and FIG. 3 is a block diagram showing the above embodiment. Figure 4 showing an example of the configuration of RAM 3 of
The figure shows an example of the configuration of the main part of the key input section of the above embodiment, Figure 5 is a flowchart showing the overall operation of the above embodiment, and Figure 6 shows the display and key sampling operation of the above embodiment. FIG. 7 is a flowchart showing the data input operation of the above embodiment, FIG. 8 is a flowchart showing the operation of obtaining the constant A of the above embodiment, and FIG. 9 is a flowchart showing the operation of obtaining the constant A of the above embodiment. FIG. 10 is a flowchart showing the operation of calculating the estimated value of x in the above embodiment. FIG. 11 shows the contents of each register in RAM 3 when specific data is input to the above embodiment. It is a state diagram showing the contents. 1...ROM, 2...ROM address section, 3...
...RAM, 4...Address section register, 5
...Operation decoder, 6...Timing decoder, 18...Arithmetic circuit, 21...Display section, 26...Key sampling decoder, 27
...Key input section, G, ~○, 2...Gate circuit, MS...Mode changeover switch, Xo...
...Key for x data input, Yo...Key for y data input, X...Key to obtain the estimated value of x, Y...Key for obtaining the estimated value of y. The key to find, AK...
...Key to find coefficient a, BK...y-intercept b
The key to ask for. Figure 1 Figure 5 Figure 2 Figure 3 Figure 9 Figure 4 Figure 6 Figure 7 Figure 8 Figure 10 Figure 11

Claims (1)

[Claims] 1. Input means for inputting numerical data, data necessary for multiple types of regression calculations including four arithmetic operations, and predetermined regression calculations serving as a reference; and regression mode designation means for specifying one of the multiple types of regression calculations; a determining means for determining whether or not the regression operation specified by the regression mode specifying means is the predetermined regression calculation; means for converting the input data to correspond to the pattern of the predetermined regression calculation and then executing the predetermined regression calculation when the regression calculation is determined to be different from the predetermined regression calculation without conversion; A small electronic calculator equipped with the following.