JPS6037560B2 - Fail memory writing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fail memory writing method, and in particular to a method in which writing positions for a reference pattern and a fail memory are made variable depending on the strobe position.

A pulse used to determine the quality of the output of an integrated circuit under test in large-scale integrated circuit testing equipment is called a strophe.

Then, as shown in FIG. 1, the strobe position has a programmable delay (Ds) position and a programmable width (Ws) relative to the instantaneous reference pulse with a programmable synchronization TCP. During the period (Ws), it is tested whether the output reference pattern and the output of the integrated circuit under test match. The output reference pattern and the input to the integrated circuit are obtained from an input/output reference pattern memory, etc., as illustrated in FIG. The address of the input/output reference pattern memory 1 is applied from the address counter 2, and the time reference pulse generator 3 issues a count command to the address counter. Further, the time reference pulse generator controls the strobe generator 4 to generate a strobe. In addition, 5 in the figure is a judgment circuit,
The output reference pattern from the input/output reference pattern memory is compared with the output of the integrated circuit under test to determine, for example, pass or fail. Next, D in the figure is an input pin driver 6, which supplies input data at a programmed level to the input of the resolution accumulation circuit. Further, C is an output pin comparator 7, which is a comparator that converts the output of the integrated circuit under test to the logic level of the system. Next, a generally used fail memory circuit based on the above is shown in FIG.

In the figure, a write control section 8, an address register 9, and a file memory 10 shown in outline are added to a conventional judgment circuit, and the output reference pattern and the output of the integrated circuit under test are compared and the judgment results are sent to the file memo river. This fail memo river ma1
This memory has a capacity of more than one bit and multiple words, and eliminates the function of writing the results of the judgment circuit. Further, the fail memory can be configured so that not only the determination result but also the output reference pattern can be written at the same time. The write address to this fill memory uses the value of the address counter of the input/output reference pattern memory as the address, and in terms of the circuit configuration, the value of the address counter 2 is transferred to the address register 9 and used as the address of the fail memory. Next, FIG. 4 shows a pulse waveform according to the above circuit configuration. As is clear from this, the output reference pattern fail memory write pulse is also at a fixed position with respect to the time reference pulse.
Therefore, the strobe program range is limited to ■ to ■. And in ■, Ds=0, and in ■, melon=TCP
-WM, N (however, WM...= strobe minimum pulse width)
Therefore, there is a restriction on the strobe delay Ds, and especially when the strobe delay Ds needs to be close to TCP, the value of TCP must be changed.
The present invention provides a fail memory write method to improve the above-mentioned conventional drawbacks.

Hereinafter, one embodiment of the present invention will be explained in detail with reference to the drawings.

First, in the time chart diagram of Fig. 5 which explains the principle, ■ is Ds=○ in the cycle where the strobe position is TCP.
, Ws=Ww, N In the TCP2 cycle, ■ is Ds=TCP2, Ws=VV
In the MINTCP3 cycle, ■ is WM, N<Ds<TCP3-WM,N, Ws=WN,N
This is the case for n.

The write pulse corresponding to the stroke of ■ is ■, but ■
The write pulse corresponding to the strobe is indicated by ■' instead of ■. Furthermore, the output reference pattern is also set to ■' instead of ■.
That is, the output reference pattern is shifted at the same time as or after the end of the strobe (2). At the same time, the fail memory write pulse is also shifted to point ■', which is a delay DF from ■'. In the figure, the strobe of ■ is Ds>WM... so ■
The strobe can be made variable up to OSDs and TCP2.

The reason why the output reference pattern is shifted to ■' is that the output reference pattern must not change until strobe ■ is completed. Next, FIG. 6 shows an example of a circuit configuration diagram.

This circuit diagram has an improved structure compared to that shown in FIG. 4 by inserting and connecting a delay circuit 11 and a selector 12 in which the output of the input/output reference pattern memory is connected in series to the determination circuit 5. First, the @ signal is a signal indicating whether the position of the strobe pulse is Ds>Ww,N, and is determined before the strobe pulse for that signal. In addition, the write control unit 8 detects Ds>WM due to the signal ■.
If N, write pulse @ is delayed by WM,N. Further, in the selector 12, when the signal (2) is Ds>WN,N, the output reference/tuning is switched to the delay circuit output side. Switching is performed at the time reference pulse position. Further, the delay circuit delays the output reference pattern by the time of N on the W side, changing ``■'' in FIG. 5 to ``■'. The method of generating the @ signal is based on the delay and width of the strobe pulse (TCP, , as shown in Figure 5).
When setting TCP2, TCP3 (which may vary equally for each time reference pulse) in the strobe pulse generator 4, it is set to "1" or "0" depending on whether or not the delay width and WN are greater than WN.
". Also, if it changes for each time reference pulse, the delay and width are written to a memory having multiple words, and this is achieved by obtaining the signal (■).Next, the above-mentioned In the example, as shown in FIG.
The address of the fail memory is the address counter of the input/output reference pattern memory, but an address counter or the like may be provided for the fail memory.

Furthermore, although the data input to the fail memory is the judgment result of the judgment circuit, the input/output reference pattern, etc. may be written at the same time as the judgment result.

As described above, according to the present invention, it is possible to write the correct judgment result to the fail memo anywhere in the range of ○ to TCP, and the strobe delay is not close to TCP and the writing to the fail memory is possible. can solve the problem of malfunction. Also, after writing a fail memo for each address of a high-speed static memory whose access time is almost equal to the TCP value, extract it and perform appropriate processing to analyze the memory failure. Can be done.

[Brief explanation of the drawing]

Figure 1 is a line diagram for explaining the strobe, Figure 2 is a circuit diagram of an integrated circuit testing device, Figure 3 is a circuit diagram of a fail memory, and Figure 4 is a line diagram showing a time chart of the circuit shown in Figure 3. 5 and 6 show one embodiment of the present invention, FIG. 5 is a diagram showing a time chart, and FIG. 6 is a circuit diagram. 1. ．． ...Input/output reference pattern memory, 2...
...Address counter, 3...Reference time pulse generation section, 4...Strobe pulse generation section,
5... Judgment circuit, 7... Comparator, 8
...Write control unit, 9...Address register, 10
...Fail memory, 11...Delay circuit, 12
······selector. Figure 1 Figure 2 Figure 4 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] 1. Apply pulses from the time reference pulse generator to the address counter, strobe pulse generator, address register, and write control section, respectively, and the address counter applies the count command it issues to the input/output reference pattern memory. Apply to the output reference pattern memory, input
The output of the output reference pattern is applied to a judgment circuit via a delay circuit and a selector connected in series together with a pulse generated by a strobe pulse generator, and the data of the judgment circuit is applied to a fail memory together with an address generated by an address register. The strobe pulse generator is equipped with a signal generation function to determine whether the strobe position is less than or greater than the strobe minimum width with respect to the time reference, and based on this signal, when the strobe position is greater than or equal to the strobe minimum width, the fail memory write position and A fail memory write method that delays the position of the output reference pattern by the time equal to the strobe minimum pattern width.