JPS6037621B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device with integrated bipolar transistors.

In recent years, there has been a remarkable increase in the density and speed of semiconductor integrated circuits, and the progress in improving the integration of MOS integrated circuits has been particularly remarkable.

In the case of bipolar integrated circuits, device isolation is required, resistive elements are required, deep buried layers must be formed to reduce the series resistance of the collector, and therefore large lateral margins are required. The reality is that the degree of integration is inferior to that of MOS integrated circuits for reasons such as the need for integrated circuits. In addition, in bipolar integrated circuits, a diffusion layer is usually used as a resistance element, but it is accompanied by a pn junction capacitance, and by providing a buried collector layer, the capacitance attached to the collector increases, etc., which contributes to high-speed operation. This is a major hindrance. By the way, the basic structure of a bipolar flip-flop used as a memory cell in a semiconductor memory device is as follows.
It consists of a pair of transistors whose collectors and bases are cross-coupled so that the collector of one is connected to the base of the other, and a load resistor that is connected to the collector of each transistor, but as mentioned above, unlike the MOS type element, Each transistor and resistor must be formed separately. In order to further increase the speed of operation, the read current from the memory cell must be increased, but in order to prevent the flip-flop from becoming deeply saturated, a nonlinear resistor is used as a load resistor. is necessary. On the other hand, it is well known that the data stored in a flip-flop is held in the form of a voltage drop across a load resistance caused by the on/off operation of a pair of transistors. It is preferable that at least the voltage drop across the load resistance is 0.4V or less. Furthermore, in order to prevent the data stored in the flip-flop from being destroyed, the voltage drop across the load resistance during data retention is required to be approximately 0.1V to 0.2V. In this way, as long as only a resistor is used as a load, only a numerical value of the holding current can be extracted from the read current. For this reason, conventionally, in order to speed up the operation, a Schottky diode is connected in parallel to the load resistor to obtain a large read current at the time of selection. However, when a Schottky diode is provided in a memory cell, the occupied area increases, which reduces the degree of integration of the device and leads to an increase in manufacturing cost. Therefore, it is necessary to carefully consider the layout configuration of the memory cells. This invention was made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that is capable of high-speed operation and that can reduce the area occupied when integrated. be.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one memory cell of a semiconductor memory device of the present invention. In the figure, Q1 and Q2 are NPN type transistors. Each of the above transistors Q1 and Q2 is connected from its base layer to its base terminal B.
However, the emitter terminal E is taken out from the emitter layer. Further, from each collector layer, a power supply terminal CP is connected via a resistor RH having a relatively high resistance value, a Schottky junction terminal S is connected via a resistor R having a relatively low resistance value, a Schottky junction element Ds, and an output terminal. Terminals Co are each taken out. The base terminal 8 of the ten thousand transistors QI is connected to the output terminal Co of the other transistor Q2, and similarly the base terminal B of the transistor Q2 is connected to the output terminal Co of the transistor QI. That is, the base terminal B and output terminal C of the pair of transistors Q1 and Q2. are cross-coupled to form a flip-flop. The power supply terminal CP of the one transistor QI is connected to one bit line BI,
Further, the Schottky junction terminal S is connected to the other bit line B2. Power supply terminal C of the other transistor Q2 above
P is connected to the bit line B2, and the Schottky junction terminal S is connected to the bit line BI. Further, the emitter terminals 8 of the pair of transistors Q1 and Q2 are commonly connected, and this connection point is connected to a word line W connected to a current sink. FIG. 2 is a plan view of the case where the above-mentioned Mori cells are integrated, and parts corresponding to those in FIG. 1 are given the same reference numerals.

Further, in the figure, the wiring running in the vertical direction is in the first layer, and the wiring running in the horizontal direction is in the second layer. Figure 3 shows the transistor QI or Q2 that constitutes the above-mentioned memory cell.
FIG. 2 is a cross-sectional view showing the element structure of FIG.

The manufacturing process for this structure will be described in detail later, but an n-type epitaxial layer 4 is grown through a localized n+-type buried layer 2 and a p+-type buried layer 3 in a p-type Si substrate 1, and an oxide film is formed. 6, 64 and the r-type buried layer 3 for element isolation,
Furthermore, using the diffusion method, the n-type collector layers 7, , 72, 7
3, p-type base layers 13, 14, n1-type emitter layer 16,
This is obtained by forming n+ type collector contact layers 17 and 18, and further providing a surface metal film 19 of the n type collector layer 7 to form a Schottky junction. Collector layer 7, 72
is separated at the surface by an oxide film 62, but internally n
They are connected by a ten-shaped buried layer 2. The Schottky junction terminal S is connected to the metal film 19, and the output terminal Co is connected to the n+ type collector contact layers 17 and 18.
A power supply terminal CP is taken out, the emitter terminal E is taken out from the n+ type emitter layer 16, and the base terminal B is taken out from the p type base layer 14, respectively. Further, the resistor RH having a relatively high resistance value is obtained by the n-type epitaxial layer 4 under the p-type base layers 13 and 14, and the resistor RL having a relatively low resistance value is obtained by the above-mentioned n-type buried layer 2. obtained by. In the memory cell configured as shown in FIG. 1, the selection current Is and the holding current IH flow from the bit lines B1 and B2 into the transistor QI or Q2. Now, the selection current Is from the bit line BI passes through the base layer via the Schottky junction terminal S of the transistor Q2, the Schottky junction element Ds, and the resistor RL, and then flows out to the word line W via the emitter terminal E. On the other hand, the holding current IH from the bit line B2 passes through the base layer via the power supply terminal CP and the resistor RH, and then passes through the emitter terminal E. Flows out to the word line W via. Here, Schottky junction element D
Due to the nonlinear characteristics of s, the selection current ls flowing from bit line BI is equal to the holding current IH flowing from bit line B2.
It can be set to a sufficiently large value compared to . That is, this memory cell has different impedance states during the holding operation and during the selection operation. For example, it is well known that in conventional memory cells, both the holding current and the selection current flow through a load resistor, so the current ratio can only be about three times as much. A current ratio of several orders of magnitude can be obtained.
Here, it is assumed that the value of the holding current IH is 24A, the value of the selection current ls is 1mA, the value of the resistor RH is 150kQ, and n memory cells are connected to the bit lines B1 and B2. When the same data is stored in the above n memory cells, a holding current of at most n×IHAA flows through one bit line, and normally this value is 10
It is around 0rA. Further, if a bit line is selected and a selection current is applied to the bit line, the bit line is charged up, and the selection current is taken out from the word line W, the selection current flows through the bit line on the opposite side to the bit line through which the holding current flows. Writing data into a memory cell is performed by changing the selection current from the bit line through which the selection current is currently flowing to the other bit line. Here, since the potential change of the bit line due to the change in the selection current is about 60 V, there is no fear that the data in the unselected memory cells will be destroyed. In addition, since a holding current always flows through the bit line, level changes in the bit line are small and high-speed operation is possible. In this way, according to the above embodiment, the distributed resistance in the collector layer 72 is used as it is as a load resistance to be connected to the collector, so unlike the conventional case, the resistance element is formed in a region separated from the transistor. The degree of integration is significantly improved compared to the conventional case.

In addition, there is no capacitance associated with the resistive element when it is formed independently of the resistive element as in the past, and there is no need to provide a buried layer over a wide area under the collector layer in order to lower the collector resistance as in the past. As shown in the figure, the buried layer 2 has a low resistance and need only be provided locally for taking out the terminal, so the capacitance associated with the collector is also reduced, and high-speed operation is therefore possible. In addition, by newly providing a shot key junction terminal, the selection current, that is, the read current, can be extracted by several times the number of holding currents, making it possible to operate at higher speed.Furthermore, only one word line is required. Therefore, the degree of integration can be further increased.Next, the manufacturing process for obtaining the structure shown in FIG. 3 will be explained in detail using FIGS. locally n-type buried layer 2 and p
An n-type epitaxial layer 4 having a thickness of about 2.5 mounds is grown through the +-type buried layer 3 {a}. This buried layer 2 is made by selectively diffusing As or Sb into the substrate, mixing a P ratio into a carrier gas, and then forming Si at 1050 pm.
It is obtained by growing the n-type epitaxial layer 4 using a specific gas pyrolysis method. After this, a silicon nitride film 5 of 3000 Å is deposited on the entire surface [W]. After this, the nitride film 5
is selectively etched away, and the exposed n-type epitaxial layer 4 is etched to a depth of, for example, 0.7 Am using a mixed solution of KOH and inpropyl alcohol 'c1.
For example, 1100 oo in wet 02 atmosphere.
, 300 minutes of oxidation is performed, and the trench is covered with a silicon oxide film 6,
, 62, 63, 64, \, n-type collector layer 7. ，
72 and 73 are formed, and then the nitride film 5 is removed and a silicon oxide film 8 is formed again by thermal oxidation, and with a photoresist mask 9 attached, boron ion is applied to the internal base formation region by 8×l and 3/3. 'd' to form a polon ion implantation layer 10. Next, the photoresist mask 9 is removed, a new photoresist mask 11 is formed, and boron ions are applied to the external base formation region at 9 times, 1×1 and 5/5 times.
Then, the whole is heat-treated at 100:00 for 20 minutes to diffuse boron from the boron ion implanted layers 10 and 12 to form a p-type internal base layer 13 and a p-type external base layer 13. A layer 14 is formed. After this, holes are opened in the emitter formation region and the collector terminal extraction region of the oxide film 8, and a polycrystalline silicon film 15 containing, for example, arsenic as an n-type impurity is deposited at 1000A by CVD.
(g). Then, this polycrystalline silicon film 15
1000 ○, 20
A heat treatment is performed for 10 minutes to form an n+ type emitter layer 16 and collector terminal extraction layers 17 and 18 (h). Finally, a hole for the base contact and a barrier hole for the Schottky junction are provided, and by vapor deposition and patterning of AI, the emitter terminal electrode 19, the base terminal electrode 192, and the three external terminal electrodes from the collector, that is, the power supply terminal electrode 19, are formed.
3. Output terminal electrode 194, Schottky junction terminal electrode 1
Complete by forming 95 (i). In this way, no special process is required when manufacturing the transistor QI or Q2.

Note that this invention is not limited to the above embodiments,
For example, in the above embodiment, a case has been described in which the memory cell is constituted by a pair of NPN type transistors, but it may also be constituted by a PNP type transistor.

As described above, according to the present invention, it is possible to provide a semiconductor memory device which is capable of high-speed operation and which can occupy a small area when integrated.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram showing an embodiment of the present invention, Fig. 2 is a plan view of the above circuit integrated, Fig. 3 is a cross-sectional view of a part thereof, and Figs. 4 a to i are its manufacture. It is a sectional view showing a process. Q1, Q2...NPN type transistor, B...
...base terminal, E... emitter terminal, CP...
...Power terminal, C. ...Output terminal, S...Schottky junction terminal, RH, RL...Resistance, Ds...
・Schottky junction element, W...word line, B1, B2
...Bit line, 1...P-type SJ substrate, 2
......n+ type buried layer, 7,,72,73...n type collector layer, 13...p type internal base layer, 14...
・p+ type external base layer, 16...Emitsuyu layer. 1st
Figure 2 Figure 3 Figure 4 Figure 4 Figure 4

Claims (1)

[Claims] 1 A collector layer separated from other regions is provided on a semiconductor substrate, a base layer is provided on the surface of this collector layer, an emitter layer is provided on the surface of this base layer, and a power terminal, an output terminal, and a shot key junction terminal are provided from the collector layer. A base terminal is taken out from the base layer, and an emitter terminal is taken out from the emitter layer, and the base terminal of one of the first and second transistors is connected to the other, and the distributed resistance in the collector layer is used as a load resistance. The base terminal and the output terminal are cross-coupled so as to be connected to the output terminal, and the power supply terminals of the first and second transistors are connected to respective first and second bit lines for providing a holding current and a selection current. The shot key junction terminal of the second transistor is connected to the second transistor,
A semiconductor memory device characterized in that the emitter terminals of the first and second transistors are connected to each of the first bit lines, and the emitter terminals of the first and second transistors are connected to a current sink word line.