JPS6037720B2 - Pulse motor drive control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse motor drive control device.

Pulse motors have been widely used in the field of machine tools for a long time, and have been recognized for their low inertia and fixed angle rotation characteristics, which are unmatched by other types of motors. It has also come to be used for carriage drives, paper feeding mechanisms, etc. By the way, there are various types of high-speed serial printers.
Nowadays, dot matrix type serial printers are attracting attention because they are relatively inexpensive and can be used as a second printer for computer output printing devices or as terminal equipment.

This dot matrix type serial printer generally has a configuration as shown in FIG. That is, in FIG. 1, a printer 1 includes a paper feed mechanism 3 that feeds a recording paper 2 upward by one print line each time printing for one print line is completed. Reference numeral 4 denotes a print head, the structure of which is as described in, for example, Japanese Unexamined Patent Publication No. 47-1.
head surface 4a.
is opposed to the line to be printed on the recording paper 2 via the ink ribbon 6.

The paper feeding mechanism 3 and the carriage 5 are driven separately by independent pulse motors. Further, this type of serial printer has recently been incorporated into a keyboard printer system as shown in FIG. 2, and the drive of the carriage 5 and paper feed mechanism 3 is also controlled from outside the printer 1. There are an increasing number of cases where

That is, the keyboard printer system shown in FIG. 2 includes a printer (PRINTER) 1 and a keyboard (KEYBO).
ARD) 7, central processing unit CPU8, storage device (RAM
/ROM) 9 and interface section (mTERFAC
Print data input from the keyboard 7 is processed by the central processing unit 8 via the interface section 10, and then transferred to the printer 1 via the interface section 10 again. Also,
The storage device 9 stores instructions or data necessary for data processing by the central processing unit 8. Further, the central processing unit 8 outputs not only print data to the printer but also function commands for the printer 1 as required. By the way, the pulse motor used as a drive source for moving the carriage 5 and paper feeding mechanism 3 of the printer 1 always requires accurate rotation amount, and the rotation speed for that purpose must also be variable in order to improve responsiveness. Must.

For example, when the carriage 5 is moved over a long distance such as when returning the carriage, or when paper is continuously fed, it is necessary to increase the rotation speed of the pulse motor to rapidly move it to the target position. When approaching , the speed must be reduced to avoid overrunning.Also, when traveling relatively short distances, low speed rotation is required. Therefore,
A variable frequency oscillator is often used to control the rotational speed of a pulse motor from a slave, and control using this oscillator is preferable for operation of a pulse motor. In other words, so-called pyramid control is performed in which the oscillation frequency of this oscillator corresponds to the rotational speed of the pulse motor, and the oscillation frequency of the oscillator is made high from start to stop until the midpoint, and then lowered. . The details of this control method are described in the public notice "Samurai Ko Sho 39-277 Group No.". By controlling the oscillation frequency of the variable frequency oscillator in this manner, the rotational speed of the pulse motor is controlled to gradually increase or decrease, that is, so-called through-up or through-down. However, the constant repetition of slew-up and slew-down of the pulse motor in this manner cannot necessarily be said to be efficient control. Therefore, although the present invention basically employs through-up/through-down control, it is intended to have a central processing unit perform more detailed optimal control. Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Fig. 3 shows the circuit of the control section in the drive circuit of the pulse motor drive control device. The controllers of the pulse motors are shown respectively. In addition, Figure 4 shows the circuit of the drive section of the pulse motor drive circuit, and since both the circuit configuration for driving the carriage 5 and the circuit configuration for driving the paper feed mechanism 3 are the same, the circuit configuration for driving the carriage 5 is shown in the drawing. Only the drive section of the pulse motor is shown.
In FIG. 3, CTR1 and CTR2 are up/down counters connected in series, the preset input terminals of which are connected to the central processing unit CPU shown in FIG. 2, and the contents of the counters are preset by the output data thereof. On the other hand, the output terminals of the counters CTR1 and CTR2 are commonly connected via inverters INVI to WV8 and resistors RI to R8, respectively, and are connected to the collector of a transistor QI of a voltage controlled oscillator VCO constituting a variable frequency oscillator. . The resistors RI to R8 have different values, and this changes the charging current through the transistor Q2 to the capacitor CI, which determines the oscillation frequency of the voltage-controlled oscillator VCO, and the unstable multipipulator MMI
oscillation frequency changes. This astable multipipulator M
The output terminals of MI are forward FWD and reverse RE of carriage 5.
Two AND gates AND1, AN for switching V
D2 is connected to each one input terminal. On the other hand, the screen is configured such that the reverse REV signal can be input to the other input terminal of the AND gate AND1, and the forward FWD signal can be input to the other input terminal of the AND gate AND2. CTR3 is an up/down counter for switching the output order of drive pulses to determine forward/reverse rotation of the pulse motor, and the output of the AND gate ANDI is the down count input terminal, and the output of the AND gate AND2 is the up count input terminal. They are connected to each input. This counter CT
The output side of R3 is separately connected to one input terminal of each of the monostable multipipulator MM2 and the AND gates AND3 to AND6 via a logic circuit LOG1 for pulse distribution. CHP is a chopper signal generation circuit, which includes an OR gate ORI which inputs the forward FWD signal and the backward REV signal, and this output and an unstable multipipeter MM3.
OR gate OR2 whose input is the output of
It is composed of an OR gate OR3 which receives the output of M3 as an input, and inverters INV9 and WVIO for inverting the respective outputs of both OR gates OR2 and OR3. Therefore,
Even if the unstable multipipulator MM3 is constantly oscillating, the output of the inverter...V9 is the forward FWD signal and the backward RE.
It becomes a chopping waveform only when there is no V signal, and is at a high level otherwise. Similarly, the output of the inverter INVIO has a chopping waveform only when there is no line feed LF signal. The output of the inverter mV9 of the chopper signal generating circuit CHP is input to the other input terminals of the AND gates AND3 to AND6. Next, CTR4 is a counter that counts the output pulses of the non-stable multipipulator MM4, and sends the output pulses to the monostable multipipulator MM5 and one input terminal of each of the AND gates AND7 to ANDI O via the logic circuit LOG2. configured to be entered.

Further, the output of the inverter VIO of the chopper signal generation circuit CHP is input to the other input terminal of each of the AND gates AND7 to ANDIO. In addition, counter CT
If R4 is constituted by an up-down counter like the counter CTR3, it is of course possible to rotate the pulse motor for driving the paper feed mechanism 3 in forward and reverse directions. Now, in FIG. 4, L1 and L2 are JI phase windings of a pulse motor for driving the carriage 5, and one ends of both windings L1 and L2 are commonly connected, and connected to the high voltage power supply HV via a resistor R9 and a transistor Q3. The terminals are connected to ground through transistors Q4 and Q5, respectively.

Further, a common connection point between the resistor R9 and the transistor Q3 is connected to the low voltage power supply LV via the diode DI. In addition, L3 and L4 are the ◇2-phase windings of the same motor, and their circuit configuration is the same as the 1-phase windings L1 and L2, with the transistor Q6
~Q8, resistor RI0, and diode D2.
The bases of transistors Q3 and Q6 are connected to the outputs ○IHC and ○ of the monostable multipipulator MM2 shown in FIG.
2HC is connected to the bases of transistors Q4, Q5, Q7, and Q8 by AND gates AND5, AND6, and A in FIG.
Each output of ND3, AND4 ◇IYC, ◇IXC, ◇2Y
C, 02YC, and Jpine C are respectively input. The drive section of the pulse motor for driving the paper feed mechanism 3 is also exactly the same as that shown in FIG. 4, and the control signal is also the AND gate AND of FIG.
7 to ANDI0, and the outputs of the monostable multipipulator MM5, and its circuit operation is similar to the circuit of the drive section for driving carriage 5, so here we will focus on the circuit operation for driving carriage 5. Explain.

The up/down counters CTR1 and CTR2 are supplied with two types of clock pulses as shown in FIG. Among these clock pulses, pulse (2) is used for through-up of the pulse motor, and pulse (2) is used for through-down of the pulse motor. Now, this counter CTR1, . If CTR2 is not preset by the central processing unit CPU, the counter output changes sequentially from the input of the clock pulse ■, and accordingly, the resistors RI to R8, which serve as the collector load of the transistor QI of the voltage controlled oscillator VCO, are sequentially switched. As a result, the output frequency of the oscillator VCO gradually increases, and when the supply of the pulse ■ stops, the count contents of the counters CTR1 and CTR2 are fixed, and the output frequency of the paralytic oscillator VCO, which receives the pulse ■, is kept constant. . Next, when the pulse ■ enters, the output frequency of the oscillator VCO gradually decreases, contrary to the pulse ■, and the counter CT
When the count contents of R1 and CTR2 reach zero, the oscillator VC
The output ◎ of O becomes zero as shown in FIG. This oscillator V
CO output ◎ is counter OTR3, logic circuit LO
The distribution pulses ◎, ■, and ■◎ are distributed through the GI as shown in Fig.
4, AND3, AND6, and AND5 are input to one input terminal each. These distributed pulses ◎ to ◎ are generated by chopper signal generation circuit C using these AND gates AND3 to AND6.
After being gate-controlled by the chopper signal (2) from the HP, it is supplied as a control signal to the drive section shown in FIG. Further, the control signals (1) and (2) shown in FIG. 5 are obtained from the logic circuit LOGI via the monostable multipipulator MM2, and these signals are also supplied as control signals to the drive unit shown in FIG. 4. Therefore, each phase winding LI to L4 is
As shown in the figure, power is supplied to drive the pulse motor. In particular, since this drive circuit excites the phase windings of the pulse motor using dual high and low power supplies, the starting characteristics of the motor are greatly improved. Also, since the hold voltage is intermittent when the motor is stopped and held at 0,
Power consumption is also reduced. Now, as mentioned earlier, in the drive control of the pulse motor as described above, it is not necessarily a good idea to always perform through-up and through-down control, but in the present invention, in order to perform optimal control of the pulse motor, When the carriage 5 moves at high speed, such as during ridge retrieval or long-distance escapement, the rotation of the pulse motor is rapidly increased.

Therefore, in the present invention, for high-speed rotation of the pulse motor, the storage device 9 stores optimal specific values as initial rotation speed data to be preset in the counters CTR1 and CTR2. Then, when the central processing unit ℃PU commands the pulse motor to start high-speed rotation, the central processing unit CPU selects the initial rotation speed from various rotation control data including the initial rotation speed data stored in the storage device 9. Deliver speed data and press counter CTR1,
Preset to CTR2 as its initial value. In this way, when the counters CTR1 and CTR2 are preset to specific values based on the initial rotational speed data from the central processing unit CPU, the oscillation frequency of the voltage controlled oscillator VCO becomes 0.
The oscillation starts at a frequency corresponding to the specific value preset in the counters CTR1 and CTR2. Therefore, the through-up time is shortened compared to when the oscillation frequency starts normal rotation from 0. In addition, when rotating the pulse motor at a low speed at a predetermined speed, the central processing unit CPU retrieves rotation control data corresponding to the predetermined speed from the storage device, forcibly presets the counters CTR1 and CTR2, and clock pulses . The pulse motor can be rotated at high speed when the carriage returns or when long-distance escapement is required. In this embodiment, the through-up/through-down control performed on the pulse motor for driving the carriage 5 is not performed on the pulse motor for driving the paper feed mechanism 3, but the motor excitation method and chopper Carriage 5 for control
It is exactly the same as that of the pulse motor for driving the
In particular, the operation of the driving circuit of the pulse motor for driving the paper feed mechanism 3 will not be explained again.

As described above, the present invention utilizes the central processing unit CPU for drive control of the pulse motor, and performs optimal control to fully utilize the characteristics of the pulse motor. The unique feature is that the rotation control data from the CPU is preset into a counter for controlling the frequency of the variable frequency oscillator, and this configuration makes the entire device extremely simple, making maintenance and inspection extremely easy. The effects of the present invention are extremely large.

[Brief explanation of drawings]

Fig. 1 is an external perspective view of a dot matrix serial printer, Fig. 2 is a block diagram of a keyboard printer system, and Fig. 3 is a circuit diagram of a drive circuit control section of a pulse motor drive control device showing an embodiment of the present invention. Similarly, FIG. 4 is a circuit diagram of the driving section, and FIG. 5 is a waveform diagram of each part thereof. In the figure, VCO is a voltage controlled oscillator constituting a variable frequency oscillator, CTR1 and CTR2 are up/down counters, CPU is a central processing unit, and LI to L4 are windings of each phase of a pulse motor. Figure 1 Figure 2 Figure 4 Figure 3 Figure 5

Claims (1)

[Claims] 1. A counter that counts up or down by a clock pulse for through-up or through-down, a variable frequency oscillator whose oscillation frequency is variably controlled according to the output of the counter, and a pulse motor that operates according to the output of the variable frequency oscillator. a central processing unit for controlling the supply of clock pulses for through-up or through-down to the counter and presetting the counter with rotation control data such as initial rotation speed data; When the counter is preset by the initial rotational speed data from the central processing unit, the oscillation start frequency of the variable frequency oscillator is made to correspond to the required initial rotational speed data to shorten the through-up of the pulse motor. Pulse motor drive control device.