JPS6037997B2 - CMOS type mask ROM - Google Patents

Description

[Detailed Description of the Invention] The present invention uses a photomask to create memory contents.
Complementary MOS logical logic storage device (hereinafter referred to as CMOS mask R)
It's called OM.

This invention relates to a CMOS type mask ROM in which the chip select decoder circuit that generates the chip select signal (2) has low power consumption, and the manufacturing process and circuit are simplified.
The ROM chip select signal has the function of selecting a chip within the ROM. In other words, only the selected chip becomes operable in response to an external signal.
The chip select signal supplied from the outside consists of one or more signals (hereinafter referred to as multi-input external chip select signals). If there are multiple signals, a decoder is used to create an arbitrary combination, and only this combination can be used. A chip select signal is generated to select a chip, and this signal enables the memory section to operate. Figure 1 shows the CMO
1 shows a conventional chip select decoder circuit that generates a chip select signal for an S mask ROM.

101 and 102 are external chip select signals CP1 and CS
2, 1 03, 1 04 are CMOS inverters, 1
05 and 106 are inverter output lines, 107 to 11
Kawama 2 input AND circuit, 1 11 to 114 are 2 input A
ND circuit output lines, 115 to 118 are N-channel transistors, 119 is a normally conductive P-channel transistor, and 12 are chip select signal lines CS, respectively.

An external chip select signal (CSI) 101 is input to an inverter 103 and one input of a two-input AND circuit 1 08, 1 10, and is connected to the other external chip select signal (CS
2) 102 is an inverter 104 and a 2-input AND circuit 10
It is in one input of 9,1 10.

The output line 105 of the inverter 103 is input to one input of the 2-input AND circuit 107, 109, and the output line 106 of the inverter 104 is input to the 2-input AND circuit 107, 109.
7,108 into one input.

Output lines 111 to 2-input AND circuits 107 to 110
114 are respective N-channel transistors 11;
5 to 118 gate electrodes.

The drain electrodes of N-channel transistors 115 to 118 are connected to a chip select signal line (CS) 120, and the source electrodes are connected to a ground line. The source electrode of the P-channel transistor 119 whose gate electrode is grounded is connected to the power supply Voo, and the drain electrode is connected to the chip select signal line 120. This circuit operates on the chip select signal line 1 for a certain combination of external chip select signals (CS1, CS2) 101, 102.
It operates so that the signal level of 20 becomes "mountain w".

At this time, the memory circuit becomes operable. A circuit for determining a specific combination includes inverters 103 and 10.
It is composed of 4, 2-input AND circuits 107 to 11. External chip select signal (CS1, CS2) 1
Table 1 shows the relationship between the levels of 01 and 102 and the output lines 111 to 114. Table 1 0: MLowM level 1: HH" level external chip select signal (CS1, CS2) 101, 1
In order for the chip select signal line (CS) 120 to be at the "Ww" level only when 02 is a combination of CSI=1 and CS2=0, the N-channel transistors 115, 117, and 118 are A configuration may be adopted in which boron ions are implanted into the gate portion to render the transistor inactive.

In this way, only transistor 116 functions as a transistor and becomes a pair with P-channel transistor 119.

As a result, the output line 1 of the 2-input AND circuit 108
12 becomes the "Hj turtle" level, the N-channel transistor 116 becomes conductive, and as a result, the chip select signal line (CS) 120 becomes the "Low" level, allowing the memory section to operate. In order to ensure a sufficient "Ww" level, the conduction resistance R of the P channel transistor 119 must be
It is necessary to ensure that P is large enough to match the conduction resistance RN of the N-channel transistors 115 to 118. C
In combinations other than SI=1 and CS2=0, the N-channel transistor 116 is non-conductive and the other transistor 116 is non-conductive.
15, 117, and 118 are also not conductive, so the chip select signal line (CS) 120 remains at the "Hj orbit" level.

In this way, the combination of external chip select signals (CS1, CS2) 101 and 102 that brings the chip select signal line 120 to the ``peak w''1 level can be selected using the gate mask. , Therefore, when the N-channel transistor conducts, the conduction resistance RP of the P-channel transistor
The series resistance RP+RN of the conduction resistance RN of the N-channel transistor is inserted between the power supply Voo and the ground.

Therefore, a current of VDo/(RP+RN) flows, and the current value is about 50 rA, assuming Voo=W, RP=100 kQ, and RN=1 blood. As described above, in the conventional chip select decoder circuit, a standby current flows when a chip is selected, so that the low power consumption, which is a characteristic of a CMOS circuit, cannot be achieved. The present invention aims to reduce power consumption by creating a circuit configuration in which no standby current flows during chip selection, and also uses a single mask to connect the gates of transistors in the chip select decoder circuit section and the memory section to the same gate. By performing ion implantation in the process, the manufacturing process is simplified and the number of circuit elements is also reduced.

This will be explained in detail below. FIG. 2 shows an embodiment of a chip select decoder circuit according to the present invention.

In this embodiment, cells in the memory section (not shown) are constructed of N-channel transistors, and other peripheral circuits (also not shown) are constructed of CMOS transistors. 201,2
02 is the external chip select signal CSI0, S20,
03,204 is a CMOS inverter, 205,206
is the inverter output line, 207 to 210 are P-channel transistors whose gates can be implanted with ions, and 21 is the inverter output line.
1 to 214 are N-channel transistors whose gates can be implanted with ions, and 220 is a chip select signal line C.
S is shown respectively.

Data is written into the memory section by implanting borosilicate ions using a gate mask. That is, a transistor whose gate part is implanted with boron has a very high threshold voltage VTN, and becomes non-conductive in normal use. At this time, in the same process, P channel transistors 207~
If boron is implanted into the gates of 210 and N-channel transistors 211 to 214, depending on the structure of the mask, an enhancement type transistor that operates normally outside the P channel transistor, and a depletion type N channel transistor that is always ON due to the implantation. There are two types of transistors: enhancement type transistors that operate normally and erase type transistors that are always OFF due to implantation. External chip selector CMOS inverter
The inverter output line 205 is connected to the gate electrode of the P-channel transistor 210 and the gate electrode of the N-channel transistor 2;4. ing.

Other external chip select signal (CS20) 202 is CM
The inverter output line 206 is connected to the input of the OS inverter 204, the gate electrode of the P-channel transistor 207, and the gate electrode of the N-channel transistor 211, and the inverter output line 206 is connected to the gate electrode of the P-channel transistor 208,
It is connected to the gate electrode of N-channel transistor 212. P-channel transistors 207 to 212 are connected to the power supply (V..) and chip select signal output line (CS) 2
20, and the N-channel transistors 211/214 are connected to the chip select signal line (C
S) 220 and ground in parallel. External chip select signal (CSI0, CS20) 201, 20
2, P-channel transistors 207/210 for the chip select signal generation circuit, and N-channel transistors 211 to 210.
Table 2 shows the combinations of No. 214 with and without a gate mask for boron immersion. Table 2 No: With gate mask for boron implantation: With: Yes Figure 3 shows the transistor configuration when a gate mask for boron implantation is prepared so that the chip is selected when CS20=0 and CSIO=1. This is what is shown.

The P-channel transistors 207 and 210 are of the enhancement type, and the transistors 208 and 209 are of the depletion type and are equivalent to resistors.

Further, N-channel transistors 211 and 214 are of enhancement type, and N-channel transistors 212 and 213 are erased. As a result,
The circuit has a 2-input NOR configuration. FIG. 4 shows an equivalent circuit in each case, and FIG. 5 shows a similar configuration using logic symbols. Therefore, only when CS20=0 and CSIO=1, the chip select signal line (CS) 220 becomes "Hi heat".
For other combinations, the level is "Low". Chip select signal line (CS) 220 is “H”
If the memory section is set to operate only when the signal is at the "i" level, it becomes possible to select the ROM chip. In Figure 6, the chip select signal becomes "High" level only when CS20 = 1 and CSIO = 1. Figure 7 shows the equivalent circuit when the gate mask for poron injection is configured as shown in FIG. In this embodiment, when the memory section of the ROM is composed of N-channel transistors, when data is written, selective ion implantation is simultaneously performed into the P-channel and N-channel transistors of the chip select decoder circuit section in the peripheral circuit to create a 2-input NOR. Creating a circuit has the advantage of eliminating standby current and lowering the current consumption of the circuit.Also, since the chip select decoder circuit is created at the same time as writing to the memory section, no extra mask is required and the manufacturing process can be simplified. There is also the advantage of simplification.
Furthermore, when comparing FIG. 1 and FIG. 2, the number of elements in FIG. 2 is smaller, and the circuit can be simplified. Moreover, the expandability of the circuit shown in FIG. 2 is better. In the first embodiment, a case was explained in which two input external chip select signals were used, but the same applies even if there are three or more external chip select signals, and in this case, a two input NOR is configured. Become. In the first embodiment, the case where the memory section is composed of N-channel transistors has been explained.
Even in the case where the memory section is composed of P-channel transistors, it is possible to achieve the same effects as in the first embodiment.

In this case, data is written into the memory section by ion-implanting phosphorus instead of boron. At this time, if phosphorus is also implanted into the gates of predetermined P-channel transistors and N-channel transistors in the chip select decoder circuit section in the same process, the mask configuration allows the P-channel transistors to be always turned off due to the enhancement mode of normal operation and the implantation. The state erasure type is divided into an enhancement type in which the N-channel transistor normally operates outside the transistor, and a depletion type in which the state is always on due to injection. FIG. 8 shows another embodiment of the chip select decoder circuit according to the present invention constructed in this manner. 807 to 810 and 811 to 814 respectively indicate P-channel transistors and N-channel transistors whose gates can be implanted with ions, and 820 indicates a chip select signal line CS.

In this circuit, unlike the first embodiment, external chip select signals (CSI0, CS20) 201, 20
The combination of 2 sets the chip select signal line 820 to "Low" level and enables the circuit operation of the memory section.

FIG. 9 shows a transistor configuration when a gate mask for phosphorus injection is prepared so that a chip is selected only when CS20=0 and CSIO=1.

In this case, the circuit has a 2-input NAND configuration. FIG. 10 shows an equivalent circuit in this case, and FIG. 11 shows the configuration of the same machine using logical symbols. When the number of external chip select signals is two or more, it becomes a multi-input NAND circuit. Since the circuit of the present invention can be easily changed by changing the gate ion implantation mask, it can be used for a control signal generation circuit in a peripheral circuit of a CMOS mask ROM, thereby reducing power consumption. .

[Brief explanation of the drawing]

FIG. 1 shows a conventional chip select decoder circuit for ROM, FIG. 2 shows a chip select decoder circuit according to the first embodiment of the present invention, FIG. 3 shows a circuit after boronion implantation, and FIG. 4 shows a circuit shown in FIG. The equivalent circuit of Figure 5 is the logic circuit of Figure 4,
FIG. 6 is an equivalent circuit related to another combination of external input select signals, FIG. 7 is the logic circuit of FIG. 6, FIG. 8 is a chip select decoder circuit according to another embodiment of the present invention, and FIG. 9 is a 10 shows the equivalent circuit of FIG. 9, and FIG. 11 shows the logic circuit of FIG. 10 after phosphorus ion implantation. 201, 202...external chip select signal line,
203, 204...Inverter circuit, 207-210...
・P channel transistors with gate masks capable of boron implantation, 211 to 214...N channel transistors with gate masks capable of boron implantation, 220, 820・
...Chip select signal line, 807-810...
P-channel transistors with gate masks capable of phosphorus implantation, 811 to 814 . . . N-channel transistors with gate masks capable of phosphorus implantation. Leopard! Figure 2 Figure 4 Figure 5 Key 6 Figure 3 Figure 3 Figure 8 Figure 9 Figure 9

Claims (1)

[Claims] 1. A memory section configured with a plurality of N-channel transistors, n input digital signals (n is an integer of 2 or more), and one combination of the n input digital signals. C, which has a chip select circuit section that generates a chip select signal that enables the circuit operation of the memory section only.
In a MOS type mask ROM, the source and drain are
2n connected in series as terminals, with one terminal connected to the power supply and the other terminal connected to the chip select signal line.
2 P-channel transistors, source and drain
2n N-channel transistors each having one end connected in parallel to the chip select signal line and the other end connected to the ground as terminals, and each gate of the P-channel transistor connected to each gate of the corresponding N-channel transistor. The odd-numbered connection points are connected to the corresponding input digital signals, and the even-numbered connection points are connected to the inverted output signals of the corresponding input digital signals, so that one combination of the n input digital signals is obtained. The P channel transistor and the N
A CMOS characterized in that half of the sets of channel transistors each have a chip select decoder circuit section each consisting of a set of depletion type P channel transistors and erasure type N channel transistors.
Type mask ROM. 2 By using a gate mask configured to selectively implant ions into the gate portion, data can be written into the N-channel transistor in the memory portion, the depletion type P-channel transistor in the chip select decoder circuit portion, and the erase type N-channel transistor. A CMOS type mask R according to claim 1, in which a transistor and a transistor are simultaneously formed.
OM. 3. A memory section composed of a plurality of P-channel transistors, n input digital signals (n is an integer of 2 or more), and circuit operation of the memory section only by one combination of the n input digital signals. C having a chip select circuit section that generates a chip select signal that enables
In a MOS type mask ROM, the source and drain are
Connected in series as terminals, one terminal after connection is grounded,
2 whose other terminal is connected to the chip select signal line.
It has n N-channel transistors and 2n P-channel transistors each having a source and a drain as two terminals, one end connected in parallel to the chip select signal line, and the other end connected in parallel to the power supply, and each of the N-channel transistors The gates are connected to respective gates of the corresponding P-channel transistors, the even-numbered connection points are connected to the corresponding input digital signals, and the odd-numbered connection points are connected to the inverted input signal of the corresponding input digital signal. and the N-channel transistor and the P-channel transistor whose gates are connected to each other so as to generate the chip select signal such that the circuit operation of the memory section is enabled only by one combination of the n input digital signals.
A CMOS characterized in that half of the sets of channel transistors each have a chip select decoder circuit section each consisting of a set of depletion type N-channel transistors and an erasure type P-channel transistor.
Type mask ROM. 4 By using a gate mask configured to selectively implant ions into the gate section, data can be written into the P-channel transistor in the memory section, the depletion type N-channel transistor in the chip select decoder circuit section, and the erasing type P-channel transistor. A CMOS type mask R according to claim 3, in which a transistor and a transistor are simultaneously formed.
OM.