JPS6040064B2 - Data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data transfer control system, and more particularly to an input/output device, a storage device for storing data transferred between the input/output device, and a storage device for storing data transferred between the input/output device. The present invention relates to a data transfer control method in a data processing system including a control device connected to an output device and to the storage device via an asynchronous bus for controlling data transfer between the input/output device and the storage device.

{Low Technology background When data is transferred between an input/output device such as an input/output device or an external auxiliary storage device and a storage device, the input/output device and the storage device are connected in order to control memory access to the storage device. A channel or an input/output control device (hereinafter collectively referred to as a channel) is provided between the two.

In fields such as minicomputers, these channels or input/output control devices are generally connected to a common asynchronous bus to transfer data to and from storage devices or to receive various commands from the central processing unit. It is configured as follows. Conventional technology and problems If the data transfer rate of the input/output bag layer controlled by the channel is slow, or if the asynchronous bus to which the channel is connected is infrequently used, the channel may be It is not necessary to provide a data buffer. FIG. 1 is a diagram showing an example of the configuration of a channel that does not have a data buffer for preventing such an overrun.

In the figure, CH is a channel, DBF is a data buffer for bus width correction, MPX is a multiplexer, U is an upper part of the data buffer DBF, and L is a lower part of the data buffer DBF. In the example shown in Figure 1, data is transferred between the asynchronous bus and the channel with a width of 2 bytes B, and data is transferred between the channel and the 1/0 bus with a width of 1 byte B. There is. Incidentally, as a trend in recent years, with the advent of high-speed input/output devices and the increased frequency of use of asynchronous buses, configurations with data buffers are increasingly being used as a method of preventing overruns.

FIG. 2 shows an example of the configuration of a channel having a data buffer for overrun countermeasures, and the data buffer is configured to have a capacity of, for example, 4 bytes B or more. FIG. 3 is a diagram showing an example of a transfer sequence at the time of a write command when searching for the configuration shown in FIG. 2. In Figure 3, D
MA is a data transfer request signal generated within the channel;
BBSY is a bus busy signal for conveying exclusive use of the bus to other devices connected to the asynchronous bus. This BBSY
Data retrieved from the storage device during the period when is on is stored in the data buffer DBF. Further, BFUL is a signal indicating that the data buffer DBF is full. When the input/output device (10) side issues a data transfer request signal SFVI, the channel side issues a response signal SRV.
Along with O, 1 byte of data in the data buffer DBF is sent to the 10 bus. In the figure, T is the minimum transfer cycle in data transfer between the storage device and the channel using an asynchronous bus, T2 is the transfer cycle of the input/output device (10), and T3 is the interval between the storage device and the input/output device. is the average transfer period of the channel, that is, the average transfer period of the channel. The following relationship exists between T and T3. T. <T3 T3≧nL (n: 1, 2, 3, ...) n is (data width of asynchronous bus)/data width of 10 bus)
is the value of

However, if the data transfer cycle on the asynchronous bus of the channel is set to the maximum transfer capacity of the channel by simply creating a buffer as described above, the frequency of use of the asynchronous bus will temporarily increase, and the transfer speed will be lower than that of the input/output device. The transfer speed is higher than that of .

This has the disadvantage of unnecessarily burdening the asynchronous bus and making system design complex and difficult. 0 Purpose of the Invention The present invention allows, when an input/output device that transfers data at a constant cycle is connected to a channel, data transfer of the channel on an asynchronous bus is performed in accordance with an integral multiple of the transfer cycle of the input/output device. The purpose of this is to average the load on the asynchronous bus and facilitate system design.

{Mura Structure of the Invention In order to achieve the above object, the present invention includes an input/output device, a storage device for storing data transferred between the input/output device layer, and an input/output device connected to the input/output device and the above-mentioned device. In a data transfer control method in a data processing system including a storage device and a control device connected by an asynchronous bus and controlling data transfer between the input/output device and the annotation storage device, the control device includes the input/output device. a counter having a count period equal to or close to an integral multiple of the data transfer period; a data buffer for temporarily holding data transferred between the input/output device and the annotation device; a data transfer control section that controls data transfer between the storage device and the control device based on an output signal issued from the counter at predetermined intervals and a signal indicating the state of the data buffer; The data transfer request cycle using the asynchronous bus between the storage device and the control device is adjusted to a value that is an integral multiple of the data transfer cycle of the input/output device or a value close to this. shall be.

N Embodiment of the Invention FIG. 4 is a block diagram of main parts of a channel in an embodiment of the present invention, in which 1 is a direct memory access (DMA) control section, 2 is a counter, 8 is a buffer control section, and 4 is a Data buffer (DBF), 5 is a preset value register, 6 is an AND circuit, 7 is a NOR circuit, 8 to 10 are inversion circuits, 11
~14 is a bus/driver circuit, CLK is a clock signal,
RST and RCTR are the reset signal and BFSET, respectively.
is the buffer set signal, and MWT is the direct memory access (
DMA) A signal indicating the direction of transfer, IRDY is a signal indicating that it is possible to write to the data buffer, ORDY is a signal indicating that it is possible to read from the data buffer, S
FTI is a response signal to the IRDY signal, SFTO is O
Response signal to RDY, RQDMA is a direct memory access (DMA) request signal, Q is a carry signal for counter 2, SDMA is a direct memory access (DMA) start signal, DMASQ is a signal indicating a direct assisted memory access (DMA) sequence, * ACTDT(i) and *ACTDT
(o) is a direct memory access (DMA) request confirmation signal;
*SFXD is a direct memory access (DMA) dominance establishment signal, *RQDT is a direct memory access (DMA) request signal, *BRSY is a signal indicating that the bus is in use, and WDBOO~15 are among the asynchronous buses. Data lines connected to the write data bus, ROMOO~15 are data lines connected to the output data bus of the asynchronous bus, PU and PL are WBDOO~15, RDBOO~15
WDBO~7 is a write data line to 10, RDBO~7 is a read data line from 10, and P is a parity line added to WBDO~7 and RDBO~7.

FIG. 5 is an example of an operation time chart when a write command is issued in the embodiment. In FIG. 5, those with the same names as those in FIG. is one data transfer period using the asynchronous bus, and T4 and L each indicate the time interval from when the RQDMA signal is issued until when the SDMA signal is issued.

The operation of the embodiment will be described below with reference to the time chart shown in FIG.

First, when a write command instructing data transfer is issued from a central processing unit (not shown), the buffer control unit 3 receives an RDY signal from the data buffer 4.
Turn on the QDN pine signal. Thereafter, when the counter 2 overflows and Q turns on, the first SDMA signal is input to the DMA control section 1, and the DMA control section 1 is activated. The DMA control unit 1 turns on the DMASQ signal and sends the ROTR signal to the counter 2.
Clear. Immediately thereafter, a preset signal (not shown) is issued, and the value of the register 5 is preset to the counter 2 as a preset value. This reset value is set to a value that is equal to or slightly smaller than an integral multiple of 10 data transfer cycles. After this, the counter 2 autonomously starts counting. Next, after issuing the DMASQ signal, the DMA control section 1 turns on the B-signal Y signal when the exclusive right of the asynchronous bus is confirmed.

Then, while this BBSY signal is on, the contents of a predetermined address of the storage device are read by a circuit section (not shown), and the read data is transferred from the asynchronous bus through WDBOO~15 to DBF4 at the timing of the BFSET signal.
Store it in Next, based on the request signal SRVI from the 10 side, 1 byte worth of data from DBF4 is taken and the data is sent to the 10 side along with the response signal SRVO.
One byte of space is left in F4. When two bytes become available, the DBF 4 sends an IRDY signal to the buffer control unit 3. As a result, the buffer control unit 3
Although a QDMA signal is issued, this RQDMA signal is not input to the DMA control unit 1 because the counter 2 is still counting. After that, when counter 2 finishes counting a predetermined period and issues a carry-Q signal due to overflow, RQ
The DMA signal is input to the DMA control section 1 as an SDMA signal.

As a result, the DMA control section 1 issues the DMASQ signal as before, and moves on to the asynchronous bus acquisition operation, and when the asynchronous bus is monopolized, turns on the B already Y signal. Then, as in the previous operation, a circuit section (not shown) reads the contents of a predetermined address in the storage device, and transfers the contents from the asynchronous bus to the W
The read data through DBOO-15 is stored in DBF4 at the timing of the second BFSET signal. 1
Data transfer using the SRVI signal and SRVO signal with the 0 device side is executed independently of the storage device access operation, and when a free space is generated in DBF4 due to this data transfer, the IRDY signal is activated as described above. will be turned on and a DMA request sequence will occur.

In the time chart of FIG. 5, in the case of the second cycle T, even if one data transfer to/from the storage device is completed and a request for the next data transfer occurs thereafter,
This shows a case where the next data transfer is pending because the counter 2 has not finished counting the predetermined time.

In addition, in the case of the third cycle of T, the DMA control unit 1
A case is shown in which the next data transfer is developed after counter 2 overflows due to a delay in monopolization of the asynchronous bus by another device (due to reasons such as the bus being monopolized by another device). In the former case, the time T4 from when the RQDMA signal is turned on to when the SDMA signal is turned on is longer, and in the latter case, the time L from when the RQDMA signal is turned on until the SDMA signal is turned on is longer. It's short. As explained above, according to the present invention, 1
Preset the counter to a value that is equal to or close to an integer multiple of the data transfer cycle of 0 (preferably a slightly smaller value), and then set it for a certain period of time (the time at which the counter overflows).
Wait before entering the DMA request sequence. Then, at the beginning of the DMA sequence (from when a DMA request is issued until the end of data transfer), the counter is reset and starts incrementing. Furthermore, if the counter has not exceeded the limit at the end of the DMA sequence, the counter is maintained until the counter exceeds the limit even if there is a request for the next DMA sequence. On the other hand, if the counter is over at the end of the DMA sequence, the next DMA sequence is immediately started. Through the above operations, the channel (CH
)'s DM-transfer cycle is close to an integral multiple of the data transfer cycle of 100, and from a system perspective, it appears that the channel (CH) performs DM-transfer at a constant cycle. Of course, due to the influence of other channels (CH),
The transfer period may be slightly longer, but this is absorbed by the data buffer. Although the above embodiment is for a write command operation, it is clear that the same operation can be performed for a read command operation (data transfer from the 10 side to the channel and further to the storage device).

Regarding the preset value of the counter, if 10 has multiple transfer cycles (for example, when a magnetic tape device processes magnetic tapes with different recording densities), the value should be changed and preset accordingly. You can do it like this. Effects of the Invention As explained above, according to the present invention, an input/output device, a storage device for storing data transferred between the input/output device, and an input/output device connected to the input/output device and the above-mentioned In a data processing system including a storage device and a storage device connected by an asynchronous bus and controlling data transfer between the input/output device and the storage device, the asynchronous method between the storage device and the control device is provided. Since the data transfer cycle using the bus is set to a value that is an integral multiple of the data transfer cycle of the input/output device, or a value close to this, the capacity of the data buffer for overrun prevention that can be provided for control clearing is large. Even so, data transfer between the storage device and the control device is performed sporadically and is not concentrated at one point in time.

Therefore, the load on the bus is reduced, which has the great effect of making system design easier.

[Brief explanation of the drawing]

1 and 2 are examples of the configuration of a subordinate channel, FIG. 3 is a diagram showing an example of a transfer sequence in the configuration shown in FIG. 2, and FIG. 4 is a main part of a channel in an embodiment according to the present invention. The block diagram and FIG. 5 are examples of operation time cheats of the embodiment. In FIG. 4, 1 is a DMA control unit, 2 is a counter, and 3 is a DMA control unit.
4 is a data buffer, and 5 is a preset value register. Figure 1 Figure 2 Figure 3 Figure 4 Dancing figure

Claims (1)

[Claims] 1 an input/output device, a storage device that stores data transferred between the input/output device, and an input/output device that is connected to the input/output device and connected to the storage device by an asynchronous bus; In a data transfer control method in a data processing system that includes a control device that controls data transfer to and from the device, the control device has a value equal to or close to an integral multiple of the data transfer cycle of the input/output device. a counter having a count period of a data transfer control unit that controls data transfer between the storage device and the control device based on the signal; and a data transfer control section that controls data transfer requests between the storage device and the control device using the asynchronous bus. A data transfer control method characterized in that the cycle is adjusted to a value that is an integral multiple of the data transfer cycle of the input/output device or a value close to this.