JPS6040069B2 - Arithmetic method for signals and trigonometric functions - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a convolution (combo IJ) calculation method used for signal processing using discrete Fourier transform, and particularly to a calculation method using trigonometric functions.

It is often used in digital signal processing for modulation and demodulation for frequency detection and transport of communication signals of this type. In particular, in telephone exchanges, in order to send and receive the digits of an incoming telephone number between exchanges, there is a signaling system in which a combination of two tones from six types of frequencies is assigned to each digit. can be used in this type of multi-frequency signal reception system.

The method of receiving multi-frequency signals using discrete Fourier transform (hereinafter referred to as DFT) is to sample the input signal at a constant period of T [seconds], and the sequence of sample values obtained is also
The sample values of the sine wave and cosine wave (reference frequency waveform) of the frequency to be detected [HZ] every T [seconds] are convolved and calculated, and the series of two types of products so, s,, s2,... co,
c, , c2, . . . (that is, si=xi×sin2 Ti, ci=xi×cos2 and Ti) are each cumulatively added for a certain period of time, and the obtained values are squared and then both are added.

The resulting value is the frequency of the input signal [HZ]
is the spectral component of Even if the input signal contains frequency components other than N, they will be erased during the calculation process. This method is known to be suitable for implementation in digital logic circuit elements since it uses only sample values at discrete points in time of the input signal. In particular, in digital exchanges in which the communication path switches are constructed with digital elements, switching is performed after all telephone signals are converted to digital codes such as PCM, so multi-frequency signals installed in this type of exchange In receivers, the Discrete Fourier Transform (DFT) is likely to be widely used.

FIG. 1 shows a conventional example of a signal detection method using the above principle. In FIG. 1, reference numerals 1 to 6 are DFT circuits that calculate six types of frequency components, ie, 6 to 6, based on DFT. First, it is assumed that an input signal is input from the input terminal 8 in the form of a PCM code. This input signal is processed by the internal block IA of the DFT circuit 1 into Sin2m〆,t and cos2〆. It is multiplied by the sample value series of t. Block IA is composed of two multiplier circuits and a code generator (or oscillator) for sin series and cos series. The next block IB consists of two adders and an accumulation memory, and accumulates the results of the previous stage. Here, when the period of accumulation is completed a predetermined number of times, the result is displayed in the next block. The signals are transferred to the block IC, and after being squared in the IC, both are added. The DFT circuit 2 also has a sin,
The cos frequency is set to N2 [HZ]. Similarly,
By providing a total of six OFT circuits with different frequencies, each component of six types of frequencies can be obtained. These D
The output of the FT circuit is input to the determination circuit 7, which determines whether each frequency component has a specified size or not. Based on this determination result, the rationality of the combination of two types of frequencies is examined, and then the The numerical information represented by the combination is obtained and output to the output terminal 9. When used as a telephone signal system receiver,
This final numerical information is transferred to the switching controller of the telephone exchange machine. In the operation of the convolution operation in the dependent example described above, the blocks IA and IB at the first stage must complete the calculation or addition within the sampling interval of the input PCM signal (usually 125 seconds). In particular, the circuit configuration of the chicken calculator is complicated due to carry processing, etc., and the operating speed is relatively slow. Therefore, in order to time-divisionally use this conventional circuit configuration and operate appropriately for a large number of time-division multiplexed PCM input signals, the calculation speed of the multiplier in the first stage block IA becomes a bottleneck. The disadvantage was that the number was severely limited. In addition, in the conventional example, many expensive quantifiers with complicated structures must be installed, which increases the price of the device.
There was a drawback that the failure rate was high. Therefore, an object of the present invention is to improve the above-mentioned drawbacks of the conventional technology, and its basic idea is to execute multiplication by using a storage device that stores product values in advance as a prime representation, and to perform convolution operations for multiple frequencies at the same time. It lies in the calculation method of signals and trigonometric functions such as execution.

The feature of the method of calculating signals and trigonometric functions according to the present invention is that N types (NZ2) of trigonometric functions are sampled at the sample interval Ts on the quantized sample value series of the input signal sampled at a constant sample interval Ts. In the calculation method of a signal and a trigonometric function to obtain a series of products obtained by multiplying the sample value series at each sampling time, the sample interval Ts and the period n of each of the N types of trigonometric functions
The period is the quotient Ms divided by the common multiples Tc and Ts for i, and the quotient M is obtained by dividing Tc by Ti corresponding to each of the trigonometric functions mentioned above.
a coefficient number generation circuit that generates a sequence of N sets of coefficient numbers incremented by step i in synchronization with a sampling pulse of an input signal; a storage circuit that stores in advance the product of the quantized sample value of the input signal and the coefficient value as a coefficient value, using the sign of the quantized sample value of the input signal and the sample order number of the coefficient value as an address; , and each time a sample value of the input signal is input, the sign of the sample value of the input signal and the coefficient number output from the coefficient number generation circuit are used as addresses to read out the seed from the memory circuit. It is based on the calculation method.

Examples will be described below with reference to the drawings. The present invention has been made to improve these drawbacks, and will be explained in detail below with reference to the drawings.

In this embodiment, CCITTNo.
．． 5 signal system and the frequency of the multi-frequency signal used in the Japan Telephone Public Corporation specification PM signal system (700,900
, 1100, 1300, 1500, 1700HZ) is shown below. FIG. 2 shows an embodiment of the invention. A time-division multiplexed PCM signal is input from the input terminal 21, and the clock terminal 22
are supplied with frame pulses and channel pulses synchronized with the input PCM signal. The format of the input PCM is 1 frame of 125 peaks (same as the sample interval), and the companded 8
It is assumed that the channel time slots of the bit codes are multiplexed into 32 channels. The sacrificial separation circuit 23 consists of a gate circuit and a series/parallel switching circuit, branches only the bottom bit (first bit) of each channel, sends it to the exclusive OR circuit, and removes the least significant bit from the remaining absolute value amplitude bits. 6 bits are provided to the multiplication table memory 24 as part of the address. The coefficient number generation circuit 25 outputs a signal indicating the segment of the memory 24 (storage circuit) in synchronization with the frame pulse and the channel pulse, and simultaneously outputs a polarity signal and transfers it to the signal 26. Figure 3 is a time chart showing the frame structure of the input PCM signal, in which one channel time slot (#0, #1,...) is further divided into 12 small time slots of 0.326 peaks, and the coefficient The number generation circuit 25 outputs an updated output for each divided time slot. These 12 small time slots are used for calculating the sin and cos coefficients of the six detection frequencies. The memory 24 is made up of a read only memory (ROM), and stores code patterns created by a method described later in predetermined segments and addresses. As a result, the code read out using the input PCM signal and the output of the circuit 25 as an address becomes equal to the absolute value of the product of the sample value of the input signal and the sample value of the trigonometric function wave of a predetermined frequency. On the other hand, the polarity multiplication process is performed by the exclusive OR circuit 26, and the result is used as an enable (operation/non-operation instruction) of the complement generation circuit 27. That is, if the polarity after multiplication is negative, the bucket number generation circuit 27 generates a tachibana number of the output code of the memory 24, but if the polarity is positive, it is passed through as is.
28 is an adder, 29 is a 32×12 circuit that goes around once in one frame.
It is a word shift register, and together they form an accumulator.

In other words, since one frame has 32 time slots and each time slot consists of 12 small time slots, the signal input to this accumulator is divided into a predetermined number of frames for each of the 32 x 12 time slots separately. The cumulative total for the period will be calculated. When the cumulative period expires, the result is sent to the next three square circuits, and the corresponding portion of the shift register is reset in preparation for the next cumulative total. To take the output from the accumulator,
This is performed by shifting each small time slot every cumulative time (for example, 2 hs) so that the timing does not overlap with each other. That is, a multiplex configuration as shown in FIG. 4 is used. The square circuit 30 can be realized by representing a multiplier or a memory storing a square code exchange table, and outputs a code corresponding to the square value of the input. A two-stage shift register 31 stores two time slot signals corresponding to sine and cos having the same frequency, and an adder 32 adds them together.

As a result, the value of each frequency component of each channel is sequentially output from the adder 32, so the determination circuit 33 compares these calculation results with a predetermined tolerance level, and if two frequencies are detected at the same time, Depending on the combination pattern, numerical information is sent out from the output terminal 34 to the outside. Now, the main points of the present invention are the multiplication table memory 24 and the coefficient number generation circuit 2.
5 is constructed as follows.

The function of this part is to output the product obtained by multiplying the input signal by using sample values of sine waves and cosine waves having six predetermined frequencies as coefficients. In the present invention, this processing is not performed by using a multiplier, but by representing a key arithmetic table prepared in advance. If the scale of this tin-combination multiplication table becomes enormous, there will be no economic effect, but we will show that this can be achieved with an extremely small-scale table by skillfully organizing the millet table method. First, the input PCM code has 7 bits excluding the polarity, and considering practical accuracy, the least significant 1 bit can be ignored.
Therefore, the number of quantized signals of the input signal is 64. On the other hand, the coefficients are sin2, Tk and cos2, i
Tk (Na i is 700,900,1100,1300,
6 species of 1500, 1700 days 2; T is 125 at sample interval
Buddha s; k is the sample number 0, 1, 2, 3,...) and Table 1
It will look like this. Table 1: Kojo Hijikawa Mioriori Angle' All chrysanthemums.

It is made of bamboo and has a small shape.

Here, we further use the formula of trigonometric functions Sin (802 bamboo) Ni Sma Sin (800) Ni - Sm8 COS8 = Sin (80) and use the Sin coefficient in Table 1 to calculate 'Ma-
m
The function between and i is as shown in Figure 5.

That is, when 0 mm < 20, j = m, when 20 mm x 60, j = 40 - m, and when 60 mm x 80, j =
It is m-80. In mZ80, this function is repeated with a period of 80. Even if the COS coefficient is small, the COS is better than the official one. Since the ground: Sinm Sanke is 0, if m in the coefficient of Sin is replaced by m + 20, m and i will be obtained for the same aircraft as above.
The relationship between is determined. From the above relationship, the sample number k and coefficient number i are as shown in Table 2 for 700Hz, for example.
Table 2 In this table, when the sample number k becomes 40 or more, the polarity of the coefficient number can be reversed and repeated.

This is because, referring to FIG. 5, the function form on the right from m=280 (corresponding to k=40) is the form with m starting from 0 with the sign reversed. Similar expansion can be done for frequencies other than 700Hz, and sample number k is 0.
By creating a coefficient number j for 39 from , the relationship between k and i can be determined by repeating the polarity inversion every 40 for larger k'.

From the above, a total of 41 types of coefficient values are required for the DFT operation for the six types of frequencies, and since positive and negative polarities are processed separately, only 21 types of absolute values of the coefficients are required.

The relationship between the previous coefficient number j and the actual coefficient is shown in FIG. Therefore, the memory 24 in the embodiment of FIG. 2 stores all the sample values (64
The products of the above-mentioned 21 types of coefficient values are calculated in advance, and these are encoded and stored in a code format convenient for subsequent processing.

During this storage, the coefficient number is used as a segment number, and the address within the segment can be accessed using 6 bits of the input PCM code. Required memory capacity is 21x64
= 1344 words, and the size of each word depends on the required calculation precision, but usually about 8 bits is sufficient. Note that the coefficient value of coefficient number 0 is 0, and any input PCM
Even if multiplied by the code, the result is always 0, so if a fixed pattern generation circuit is added that outputs an output code equivalent to 0 without accessing the memory for this coefficient number 0, the memory 24
The required capacity can also be reduced to 20x64 words. The coefficient number generation circuit 25 is configured, for example, as shown in FIG.

In FIG. 7, a frame pulse received from the cook terminal 22 is input to a 4G ship counter 71, and a channel pulse is input to a multiplier circuit 72 to generate one channel time.
generates timing pulses that divide the time slot into 12 small time slots. 73 is a hexadecimal counter which outputs a count value in synchronization with the small time slot.

Reference numeral 74 denotes a memory exclusively for discussion, consisting of a memory of 12×40 words.

Since each word is for storing coefficient number j, it is sufficient to have at least 6 bits. Counting output 7 of 4-man counter 71
1A and the count output 73A of the hexadecimal counter 73 are used as addresses to access the memory 74.

This memory stores the coefficient number i, address contents 71A correspond to the sample number k, and 73A is used to identify sine waves and cosine waves of six types of frequencies. The memory 74 stores Tables 2 and 7 corresponding to these addresses.
A similar table for frequencies other than 00Hz is written in advance as shown in FIG. The inversion circuit 75 consists of a flip-flop that generates an inversion pulse every time the counter 71 exceeds 40. Using this output, only the polarity bit of the sign of the read content of the memory 74 is determined by an exclusive OR circuit 76 every 40 frames. The polarity is reversed and sent to 26. On the other hand, portions of the output from the memory 74 other than the polarity are transferred to the memory 74 . FIG. 9 shows another embodiment of the coefficient number generation circuit 25, in which the amount of memory is reduced at the cost of making the counter circuit slightly more complicated.

That is, in Table 2, the sine coefficient k = 20 or more is symmetrical to k = 19 or less, and the cosine coefficient is sine
By utilizing the fact that the coefficient k is equal to the sequence obtained by shifting it by 20, the overlapping parts can be omitted and the sequence shown in FIG. 10 can be obtained. In FIG. 10, the mark ◎ indicates the starting position, and the dotted line indicates polarity reversal. 1st
As shown in Figure 0, by changing the reading order for sine coefficient numbers and cosine coefficient numbers and shifting the timing of polarity reversal, the amount of memory for specifying coefficient numbers is reduced by 1' compared to the first embodiment. It can be set to 4. In Figure 9,
A terminal 91A receives a frame pulse, and 92 and 93 are two-way counters. The counter 92 is an up counter whose initial value is 0 and the count value increases by 1, and the counter 93 is a down counter whose initial value is 20 and decreases by 1. Both counters return to their initial values after counting 2 solid pulses. 94 and 95 are two-stage flip-flops that count the number of turns of the counter 93.

A selector 96 selects one of the count output values of the two counters 92 and 93 and supplies it to the memory 98 as part of the address.

On the other hand, the state 91B receives the channel pulse and the telemultiplier circuit 1
00 divides this channel time slot into 12,
Create a small time slot pulse. 101 is a flip-flop, and 102 is a hexadecimal counter.

The selector 96 has two flip-flops (FF) 94
The output is selected by a combination of the output values of and 101.

As shown in the time chart of Fig. 11, FF94 is 2
It is inverted every 0 frames, and FFIO1 (switching between sine and cos) is inverted every small time slot, so when the two states match, the value of the counter 92 is output as the output of the selector 96, and when they do not match, the value of the counter 92 is output. outputs the value of the counter 93. In other words, FF94 switches from the top to the bottom of the table in FIG. 10, and FFIO
I is switching between sin and cos. Regarding polarity processing, another flip-flop 95 is placed after the FF 94, and control is performed by a combination of the FF 94 and the FF 95. That is, referring to the dotted line in FIG. 10, s
Regarding the in coefficient, in the third and fourth large frames (a large frame is defined as a fixed frame period of 2), the gutter nature of the code extracted from the memory 98 is reversed, and cos
The coefficients are inverted between the first and fourth large frames. The count of large frames can be known from the outputs of FF94 and FF95, and also from the outputs of FFIO1 (sin and c
The logic circuit 97 generates a polarity inversion instruction by combining the outputs of the OS switching). The memory 98 is a read-only memory, and the memory 98 is a read-only memory, and the memory 98 is a read-only memory.
The value of j′ is stored at the address of ′. The selection of the address of the frequency location in this memory is determined by the hexadecimal counter 1
02 (frequency switching). The required capacity for this memo is 6 x 21 words. (One word requires at least 6 bits) Gate 99 is an exclusive OR circuit for inverting the polarity bit. As explained above in Table 3, the memory 24 stores a multiplication table containing only absolute values excluding polarity, and the polarity arithmetic processing is separately added to the output of the memory 24.

However, in the method of implementing the present invention, it is not necessarily necessary to separate and treat the gutter properties. In other words, the size of the memory 24 can be further increased, and the input PCM signal and coefficient number can be used as the address of the memory 24 with polarity, and the calculated value to be stored in the memory can also have polarity. In this case, as shown in FIG. Various circuits 23, 26, 2 related to polarity processing in
7 is unnecessary. However, the capacity of the memory 24 becomes larger. Therefore, the structure of the multiplication table memory and coefficient number generation circuit according to the present invention can be implemented in various ways by developing the structure as described below. Figure 12 shows the method of creating a multiplication table memory, and shows the waveform W' or Sin journal (M rut value).
shall be. This memory is represented by the input PCM code and the number (coefficient number) m of the sample value of the waveform W, and the product of the input value and the sample value of the waveform W is stored in each address position. Since the waveform W repeats every time m changes by 2, it is equal to mi reference wave periods ni. Since the phase for one period is 2 m radian, the sample interval Ts for the common period Tc
When converted into a phase change, PC = young x object = solution.

On the other hand, the phase change of the sampling interval Ts with respect to the reference wave period Ti is as follows: Pi=band X2bamboo=crocodile xmi, and pi=PC×mi.

Therefore, it can be seen that the sample value of the reference wave can be obtained by sampling a sine wave having a common period Tc at Ts, and using the sample value every mi sample values. Also, considering the symmetry within one period of a sine wave, as explained in Figure 12, the Fujimoto value for the entire period is not necessarily necessary, but even for half a period or a quarter period. good. If the smallest common multiple is adopted as the common multiple Tc, ms
This method requires the least amount of data and is advantageous in terms of implementation. Furthermore, since the cosine function of the reference wave is equal to the sine function whose phase is shifted by 1/2, when using the sample value of the common period, the sample number may be shifted by ms/4.
However, if ms is not a multiple of 4, either set Tc large so that ms is a multiple of 4, or separately sample a cosine wave with a period of Tc for the cosine function using Ts, and divide the sample value into mi pieces. You can use it every time. For the six reference frequencies (700-1700Hz) in the above example, Ts=1/
800 seconds, Tc=1/100 seconds, mS=80 m,=7
, m2=9,..., m6=17.

As explained above, the present invention realizes the input signal and reference trigonometric function convolution calculation unit, which required the most complex and high-speed elements in conventional implementation circuits, using a combination of read-only memories without using a multiplier. This has the advantage of simplifying the configuration and making it easier to operate at higher speeds.

The type of memory used in the present invention is suitable for a high degree of integration, has a simple structure, is highly reliable, and consumes little power. Furthermore, since the element is versatile, mass-produced products can be used, resulting in low cost. As shown in the example, even for sine wave/cosine wave calculations for 6 frequencies, with the minimum configuration, it is sufficient to use the range from -40 to 140 as shown in the figure. be. Therefore, the most basic memory map of the present invention is as shown in FIG.
This includes the positive/negative sign and the entire range of one cycle of the waveform W. In this case, for example, for 700Hz calculation,
The coefficient number address m may be incremented by 7 and repeated cyclically as shown at 1 in FIG. 12. If you store the value including the polarity in the memory,
There is no need to perform magnetic processing on memory output. As a method to reduce the size of this basic multiplication table memory vertically, 2.
Both methods can be applied separately or in combination.

The first method is to separate the polarity of the input PCM code. In other words, by using only the absolute value as the address of the chicken balance sheet memo, the memory size is halved. Then, it is necessary to perform an operation that sacrifices the input time to the memory output. (In other words, leave it as is for positive input,
(Reverses polarity for negative input). The second means takes advantage of the internal symmetry of the waveform W. As shown in Figure 12, m is from -20 to 120, and m is ±20.
Each time the boundary is crossed, the direction is reversed and the address is incremented. Memory will be half the size. Furthermore, as another method of the second means, m uses a range from 0 to 120, as shown in m in FIG. , the memory output sacrifice is reversed every time it wraps around 0. At this time, the memory capacity is further halved. In the embodiment shown in FIG. 2, this first
and m of the second means are used.

It is clear that other combinations can be easily realized. In the above embodiment, the reference frequency is 700 to 1700.
Although the explanation has been given using six HZ frequencies as an example, the present invention can be practiced without being limited to these frequencies. The frequency can be generalized and explained as follows. Let Ts be the sampling interval, and let Ti (i=1, 2, . . . N) be the reciprocals or periods of N types of reference frequencies N [HZ]. Let Tc be the common multiple for Ts and all Ti, then ms, m
When i is an integer, Tc=mS×TsTc=mi×Ti.

That is, the common multiplier period c is divided into ms sample intervals Ts, and the common multiplier period Tc is 21×64×8;
10,752 bits and 21×6×6=756 bits are sufficient, and recent LSI memory elements can be accommodated in one or two chips. If the cycle time is also 326 nanoseconds, 32 channels can be time-division multiplexed. As described above, it is clear that applying the present invention to digital signal processing such as DFT has a very large effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a DFT according to a conventional example, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a time chart showing a time division multiplexing configuration of the embodiment, and Fig. 4 shows the cumulative time. 5 is a graph showing the relationship between the general form of the sample number and the coefficient number, FIG. 6 is a graph showing the relationship between the coefficient number and the coefficient value, and FIG. 7 is a first implementation method of the coefficient number generation circuit 25. 8 is a memory map showing the allocation of the memory 74, FIG. 9 is a block diagram showing the second implementation method of the coefficient number generation circuit 25, and FIG. 10 explains the operation of FIG. 9. FIG. 11 is a time chart for explaining the operation of FIG. 9, and FIG. 12 is an explanatory diagram of a method for creating a multiplication table memory. 21... Input terminal, 22... Clock terminal, 23... Polar division key circuit, 24... Multiplication table memory, 25... Coefficient number generation circuit. , 26...
8E Alternative OR circuit, 27... Complement generation circuit, 28... Adder, 29... Shift register, 30... Self-elementary circuit, 31... ...2-stage shift register, 32...Adder, 33...
Judgment circuit, 34... Output terminal. Kago no zu, 2nd figure, 3rd figure, different figure, 4th groove, a collection of interesting drawings, 3rd figure, 8th groove? Figure '0 figure exclusively Figure eagle r2 figure

Claims (1)

[Claims] 1. Predetermined N types (N≧2) of trigonometric functions are sampled at the sample interval on a quantized sample value series of an input signal sampled at a constant sample interval Ts. In the method of calculating signals and trigonometric functions to obtain a series of products obtained by multiplying the sample value series at each sample time, the common multiple Tc for the sample interval Ts and the period Ti of each of the N types of trigonometric functions is defined as Ts.
The period is the quotient Ms divided by , and the quotient Ti, which is obtained by dividing Tc by Ti, is increased as a step corresponding to each trigonometric function.
a coefficient number generation circuit that generates a sequence of coefficient numbers of a set in synchronization with a sampling pulse of an input signal; A storage circuit is provided in which the product of the quantized sample value and the coefficient value is stored in advance using the sign of the quantized sample value of the input signal and the sample order number of the coefficient value as an address, and the sample of the input signal is An operation between signals and trigonometric functions, characterized in that each time a value is input, the product is read from the storage circuit using the sign of the sample value of the input signal and the coefficient number output from the coefficient number generation circuit as an address. method. 2. In the method of calculating signals and trigonometric functions according to claim 1, the common multiple includes the Ts and each of the Ts.
An arithmetic method for signals and trigonometric functions characterized by using the least common multiple of i. 3. In the method of calculating signals and trigonometric functions according to claim 1 or 2, the coefficient number generation circuit is configured such that the generation of the coefficient numbers increases by Mi in the first half of the period Ms and decreases by Mi in the latter half. A method for calculating signals and trigonometric functions, characterized in that the storage circuit stores the product regarding a half period of the common multiple Tc at the address. 4. In the method of calculating a signal and a trigonometric function according to claim 1 or 2, the coefficient number generation circuit generates the coefficient number M in the first and third quarters of a cycle Ms.
The circuit increases by i, decreases by Mi in the second and fourth quarters, and generates a polarity inversion signal in the third and fourth quarters, and the memory circuit stores the product of the quarter period of the common multiple Tc in the address. A method for calculating signals and trigonometric functions, characterized in that the storage circuit stores the data, and further includes a polarity inversion circuit for inverting the polarity of the output of the storage circuit when the polarity inversion signal is generated and outputting it. . 5. In the method of calculating a signal and a trigonometric function according to claim 1, 2, 3 or 4, the storage circuit stores the absolute value as the product of the sign of the quantized sample value of the input signal. a polarity of the input signal and a sample order number of the coefficient values are stored in advance as an address, and a polarity separation circuit is provided in front of the storage circuit to separate the polarity of the input signal and send only the absolute value to the storage circuit. and a polarity synthesis circuit for adding the polarity separated by the polarity separation circuit to the output of the storage circuit is provided immediately after the storage circuit. 6. In the method of calculating signals and trigonometric functions according to claims 1, 2, 3, 4, or 5, when a sine function and a cosine function of the same period are included among the N types of trigonometric functions,
The method for calculating signals and trigonometric functions, wherein the coefficient number generation circuit generates coefficient numbers as a mutual difference Ms/4 between the sine function and the cosine function.