JPS6040220B2 - semiconductor switch control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a low-power gate control circuit that turns on or off an integrated semiconductor switch circuit using only a control signal.
Alternatively, the present invention relates to a semiconductor switch control circuit capable of both on and off control.

Conventionally, many types of semiconductor integrated switches have been put into practical use, including a current-driven integrated PNPN switch shown in FIG. 1, for example.

Here, 1 is PNPN switch, 2' Mad Gunmatsu. circuit,
3 is a first gate drive circuit for ON control, 4 is an ON state holding memory, 5 is a main current cutoff control circuit as an external circuit,
6 is an inverter, 7 is an external switch for main current cutoff, RL
is the load impedance, D1, D3 are diodes, K is the power sword, A is the address, X is the X address, Y is the Y address, ME is the memory enable signal, Vc is the switch control input signal, IM^IN is the main It is the circuit current. In the group plow o circuit 2, when a pulse voltage is applied to the main current circuit when the switch 1 is in the cutoff state, the displacement current of the junction capacitance flows into the gate, and the switch 1 can be easily cut off to the conductive state. It was set up so that it would not occur.

The on-state holding memory 4 maintains the on-state of the switch even after the current once becomes zero when the main circuit current is alternating current or pulse, and is used by arranging integrated switches and NPN switches in a matrix. In this case, the number of control signal terminals is reduced by applying a common on/off control signal to the switch at a specific address position using the X and Y addresses of each switch and the memory enable signal M. be. P which is the switch body
NPN switch and its control circuit 3 and diode D
1 and D3 are integrated on the same semiconductor chip. Further, as shown in FIG. 1, the cutoff of the switch 1 is performed by the external circuits 5 and 7 for the semiconductor chip described above, and the main current cutoff control circuit 5 and the external switch 7 are configured to forcibly cut off the main circuit current. It had been. Integrated PNP in Figure 1
In the N switch circuit, in order to switch the PNPN switch from the cutoff state to the conduction state, it is necessary to draw current from the N gate NI or to flow current into the P gate P2. The gate drive current Ion,N flowing out from the P gate P2 or the gate drive current ION,P flowing into the P gate P2 is controlled by the switch control input signal Vc via the control circuit 3.

Note that whether the N gate NI or the P gate P2 operates depends on the cathode potential VK of the path of the main current IM^...
It is determined by the potential relationship between the control circuit power supply V and the control circuit power supply V. Conventionally, the gate drive circuit 3 that causes the transition in the opposite direction, that is, the transition from the conduction state to the cutoff state, has not been integrated for the reasons described below, and the cutoff of the PNPN switch flows to the switch 1. By cutting off the current itself via the external switch 7, the configuration is such that the external circuit 5 is completely separate from the integrated INPN switch.

The reason why integration of the off control circuit could not be realized is that the power consumption of the off control circuit increases. Here, set the PNPN switch 1 to P as shown in the first diagram.
When considered as a composite of two types of transistors, NP and NPN, both transistors in a PNPN switch in a conductive state are generally in deep saturation, and the current amplification factor is much smaller than the value in the non-saturated state. There is. In order to cut off the base current of an NPN (or PNP) transistor in such a state by drawing out (or injecting it into) the transistor, the main value flowing through the PNPN switch must be divided by the current amplification factor that has decreased in the saturated state. This value is much larger than the base current needed to transition to the conductive state. Therefore, the power consumption of the off control circuit becomes large, and integration is not possible. For the above reasons, an integrated PNPN with a function of interrupting the main circuit current IM...
Although switches have not yet been put to practical use, it is desirable in use to be able to perform both the conduction and cutoff functions of the main circuit current IM with the same control signal, and its realization has been awaited.

Note that a gate turn-off (GTO) type thyristor is conventionally known as a switch that has the functions of both conducting and cutting off the main current using the same control terminal.
In this case, the gate terminal is simply taken out as a control terminal, and integration including a control circuit has not been realized. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a PNPN which can perform both main current conduction and cutoff functions using the same control signal input, has low power consumption, and is suitable for integration.
An object of the present invention is to provide a control circuit for a semiconductor switch such as a switch.

Another object of the present invention is to provide a semiconductor switch control circuit suitable for integration on the same semiconductor substrate with a semiconductor switch such as a PNPN switch.

To this end, the present invention provides a monitoring circuit for the conduction and cutoff states of a semiconductor switch, such as an integrated INPN switch, to detect the switch state, and sends the detection output to a gate drive current ON control circuit and OFF control circuit, respectively. The OFF control circuit and the ON control circuit are disconnected in a steady state after the state transition is completed, and the gate drive current is configured to flow transiently during the state transition.

Furthermore, in the present invention, the above-mentioned monitoring circuit and on/off control circuit are formed on the same semiconductor substrate as the PNPN switch. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows an example of the configuration of an integrated NPN switch control circuit according to the present invention. The on-state holding memory 4 shown in FIG. 1 is not directly related to the present invention, and it is possible to hold the on-state by using a logic level such as a TTL signal as the switch control input signal Vc, so it is not shown here. It has been omitted. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and their details are omitted. In the figure, 8 is a main current monitoring circuit, 9 is a second gate drive circuit for off control, 10 is an inverter, D2, D4 are diodes, RL, 2 is a load impedance. Main current circuit potential and control circuit 3
Whether the N gate NI or the P gate P2 of the switch 1 operates is determined by the relationship between the power supplies 1V and -V2 of the switch 1 and the power supply 9.

The switch control input signal Vc and the reverse phase control input signal Vc via the inverter 0 are supplied to the second gate drive circuit 9 and the first gate drive circuit 3, respectively. When the P-gate P2 operates, the on-current ION,P is injected from the first gate drive circuit 3 to the P-gate P2 via the diode DI, and when the P-gate P2 is off, the second gate is driven from the P-gate P2 via the diode D4. Off current lo to circuit 9
FF and P are pulled out. On the other hand, when the N gate NI operates, the second gate drive circuit 9 drives the diode D2.
An off current loFF,N is injected into the N gate NI through the diode D3, and an on current ION,N is extracted from the N gate NI to the first gate drive circuit 3 through the diode D3. The main current monitoring circuit 8 detects whether the PNPN switch 1 is in a conductive state or a cutoff state, and outputs binary detection signals SI and S2 according to the detected state, and gates in a steady state. This is for supplying detection signals SI and S2 to gate drive circuits 3 and 9, respectively, so that the drive current becomes zero. By providing the main current monitoring circuit 8, the on-gate current ION. P or I
ON. N and off-gate current loFF. P or lo
By passing pP,N transiently only during the transition period of the switch, the average power consumption of the control circuits 3 and 9 can be reduced, and in particular, it is possible to integrate the OFF control circuit 9. Note that if the potential of the main current circuit of the PNPN switch 1 is always at a positive potential or always at a negative potential, only one of the gates will operate, so the input of one gate should be omitted. I can do it.

For example, when the PNPN switch 1 is used in a circuit in which the cathode K side of the main current circuit is connected to the atmosphere through a load impedance R, and the anode A side is connected to a negative power supply through a load impedance RL2,
Off current loF to N gate NI via diode D2
F. The on-current ION.N flows through the current path and the N gate NI through the diode D3. The current path for drawing out N can be omitted. A typical example of such usage is a switch inserted into a circuit that supplies communication current from an exchange to a telephone subscriber line. In this case, the cathode K side of the PNPN switch is connected to the earth through the load impedance RL, while the anode A side is connected to the -48 volt local power supply through the load impedance RL2, and the PNPN switch 1 always operates on the negative potential side. . FIG. 3 shows an embodiment of the present invention intended for the usage described above, where RI to RII are resistors, D5 to D14 are diodes, and QI to Q18 are transistors.

A TTL signal is used as the switch control input signal Vc. GND is the ground potential. In this example, a local power supply of -48 volts, which provides the lowest potential in the main current circuit, is used as the negative power supply for the circuit that extracts the off-gate current loFF,P from the P gate P2. In FIG. 3, portions corresponding to the blocks in FIG. 2 are shown surrounded by dotted lines. The operation of this circuit will be explained.

First, a case will be described in which the main circuit currents lwA,N transition from a state in which they are not flowing to a conductive state. Here, TTL
The logic level switch control input signal Vc is at a low level (L
) to a high level (H). Due to this change, the base potential of transistor QI rises, turning on transistor QI, lowering the base potential of transistor Q5, turning off transistor Q5, and raising the base potential of transistor Q7, turning on transistor Q7. , a current determined by the emitter resistor R7 of the transistor Q7 flows through the collector of the transistor Q7.
This collector current flows into the P gate P2 of the PNPN switch through the diode DI as the collector current of the transistor Q8 by a current mirror consisting of diode-connected transistors Q6 and Q8, thereby turning the PNPN switch 1 into a conductive state. Furthermore, when the main circuit currents IM^, N flow through the PNPN switch 1, the transistor Q15 of the main current monitoring circuit 8 is turned on, and the current determined by its emitter resistance RII flows through the current mirrors Q14, Q13, thereby causing the resistance RI This voltage drop occurs, and this voltage drop causes transistor Q
16 is turned on. The collector current of transistor Q16 causes a voltage drop across resistor R12, and detection signal SI is generated. This detection signal SI causes the transistor Q17 to
is turned on and the current of the current mirror diode-connected transistor Q6 is bypassed to the transistor Q17, thereby cutting off the collector current of the current mirror transistor Q8, that is, the on-gate current Ion,P. As a result, the on-gate current I flowing into the P gate P2
ON, p is actually cut off at the same time as the main circuit current IM^... flows, and only flows in a pulsed manner. On the other hand, in the case of transition from the conductive state to the cut-off state, the TTL control input signal Vc changes from high level (H) to low level (L),
Transistor QI is turned off and transistor Q2 is turned on, driving current mirrors Q3 and Q4. The output current of this current mirror transistor Q4 further drives current mirrors Q9 and QIO on the negative potential side. In order to suppress the power consumption of the off control circuit 9, the mirror ratio n is set to 1 or more in the current mirror Q9, QIO at the final stage, and a relatively large off-gate current loFF, P is generated at the final stage. Transistor QIO is connected to P through diode D4.
Off-gate current l from P gate P2 of NPN switch 1
Pull out oFF, P and turn the switch to the cut-off state. As a result, when the main current IM^, N is cut off, the transistor Q15 of the main current monitoring circuit 8 is also turned off, and the current mirrors Q14, Q13 and further transistor Q12 are turned off.
is also turned off. Subsequently, the transistor QII turns on, resulting in a detection signal S2, which
2 causes a voltage drop across the resistor R14, turns on the transistor Q18, and bypasses the current flowing through the diode-connected transistor Q3 of the current mirrors Q3 and Q4. This cuts off the output currents of current mirrors Q3 and Q4, and also cuts off the currents of current mirrors Q9 and QIO. As a result, the off-gate current loFF,P automatically returns to zero and only flows in a pulsed manner. The temporal relationship among the TTL control input signal Vc, the on-gate current ION,P, the off-gate current loFF,P, and the main circuit current IM^... is schematically shown in FIG. 4. As explained above, according to the present invention, by feeding back the output of the main current monitoring circuit to the gate on/off drive circuit in a PNPN switch, the gate drive current flows only during the transition period when the state of the switch changes. In this way, it can operate with low power consumption and perform both on and off functions with a single control input signal.

According to the present invention, it is possible to achieve the integration of an OFF control circuit, which has been difficult to realize in the past, and an easy-to-use integrated NPN switch can be realized, since an external circuit for turning off the switch is not required.

Note that in order to turn on and off multiple PNPN switches simultaneously using the same control input, the on-gate current,
The output transistor of the current mirror in the final stage that generates an off-gate current, for example, in FIG. 3, a plurality of transistors Q8 and QIO are arranged, and each transistor is connected through an appropriate diode (diodes D1 and D4 in FIG. 3). The gates (P gates in FIG. 3) of a plurality of PNPN switches may be driven by using the PNPN switch. In addition, according to the present invention, both the on-control current and the off-control current are automatically restored after a state transition, so when conventional gate driving is performed using current or voltage pulses, There is no need to consider the margin of drive pulse width that was required in the previous example, and the design of the peripheral circuit system becomes easier.

In addition, in the above, SCS (Silicon Control)
Although the present invention has been described using an example of a PNPN switch of the type SCR,L
ASCR (Light Activated SCR)
, GTOSCR, TRIAC, and other semiconductor switch drive circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an example of a configuration of a control circuit for a slave integrated circuit and an NPN switch, and FIG. 2 is a circuit block diagram showing an example of a configuration of a control circuit for an integrated circuit and an NPN switch according to the present invention. FIG. 3 is a detailed circuit diagram showing the configuration of a specific example of the present invention, and FIG. 4 is a schematic diagram showing time changes of the control signal, gate current, and main circuit current. 1. ．．・-．・PNPN switch, 2-. ．． ．． ．． ．． d Tsunematsu. Circuit, 3...First gate drive circuit for ON control,
4... ON state holding memory, 5... Main current cutoff control circuit, 6. ．．・...Inverter, 7...
... External switch for main current cutoff, 8 ... Main current monitoring circuit, 9 ... Second gate drive circuit for off control, 10 ... Isoverter, RL, RL, ,RL
2...Load impedance, RI~RI1...
...Resistance, DI~D14...Diode,
QI~Q18...transistor. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A pair of anode and cathode and at least one gate are provided, and by applying a gate control signal to one or more of the gates, the impedance between the anode and the cathode is low impedance. Further, the bistable structure is configured to switch to high impedance and maintain the impedance between the anode and cathode in a low impedance or high impedance state even when the gate control signal is not applied. In a semiconductor switch control circuit that controls a semiconductor switch, a first detection signal is sent when the semiconductor switch transitions from high impedance to low impedance, and a second detection signal is sent when the semiconductor switch transitions from low impedance to high impedance. a state detection circuit for providing a first gate control signal to set the semiconductor switch in a low impedance state in response to a first level switch control signal; a first gate drive circuit for stopping supply of the first gate control signal in response to the first gate control signal; and a second gate control signal for setting the semiconductor switch in a high impedance state in response to the switch control signal at a second level. 1. A semiconductor switch control circuit comprising: a second gate drive circuit configured to supply a second gate control signal and stop supplying the second gate control signal in response to the second detection signal sent out thereafter.