JPS6040265B2 - Overvoltage suppression circuit for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an overvoltage suppression circuit for suppressing overvoltage generated by wiring inductance during switching of semiconductor elements in a conversion device such as an inverter that is composed of a plurality of semiconductor elements. .

Conventionally, an R-C circuit consisting of a resistor, a capacitor, etc. has been used as a circuit to prevent overvoltage in this type of semiconductor device. It is hoped that it can be manufactured at a low cost.

Figure 1 shows a typical conventional overvoltage suppression circuit for semiconductor devices, which includes transistors T, , T2, and T2.
3. In an inverter circuit in which T4 and diodes D, D2, D3, and D4 are bridge-connected to a variable DC power source Ed, each diode D. ~ In parallel with D4, i.e.
An RC series circuit (encircled by a broken line) consisting of a resistor Rs and a capacitor Cs is connected in parallel between the emitter and collector of each transistor T, -T4.

Although FIG. 1 shows an inverter made up of transistors T, -L, it goes without saying that the same applies when semiconductor switching elements such as thyristors or gate turn-off thyristors are used. Also, ld is the wiring inductance of the hypothetically shown power supply circuit, and Z
indicates the load. However, R- shown in FIG.
The operation of the C series circuit is as shown in FIG.

In other words, if the transistor T turns off at time t, the transistor T operates smoothly until time t.
, overvoltage is suppressed (Fig. 2 1). Further, from time t5, the transistor T3 is turned off, and in this case as well, the same overvoltage suppressing effect as that of the transistor T can be obtained (FIG. 2, 5). In addition, Fig. 2 1
The waveform shown by the broken line in is the voltage waveform when no R-C series circuit is provided. However, the circuit shown in FIG. 1 has the following drawbacks.

1. An RC circuit is required for each semiconductor element (transistor), increasing the number of parts.

2 The capacitor (CS, for example) of the R-C circuit is connected to the second
As shown in Figure 3, charging and discharging are performed every time the semiconductor element switches, so as the switching frequency increases, the loss caused by the series-connected resistors (for example, voltage Rs) becomes extremely large, resulting in higher costs. .

In order to eliminate the above-mentioned drawbacks, as shown in Fig. 3, a discharge blocking type R-C-D circuit of a series arm lump type is constructed, in which a diode DS is connected in parallel with the resistor RS to a series circuit of a resistor Rs and a capacitor Cs. It is proposed to use the area (encircled by a broken line).

According to this circuit, the configuration is simple, compact, and low cost, but in addition to the wiring inductance ld of the power supply circuit, there are also inductances 1, to 16 between the transistors T and T4, and the R-C-D circuit. There is an inductance IS etc. Therefore, as shown in FIG. 4, the operation of the circuit shown in FIG.
V(IS)=I according to the change in the charging/lowering flow i(CS) of s
An excessive voltage (vcEp>
vcEm) (Fig. 4, 1). In addition, if the inverter is a 4-capacity model, the device itself is small and the 1, to 16 or ls can be made small, so the effect is small (the waveform shown by the broken line in Fig. 4 1), In the case of a large-capacity model, the effect becomes large (as shown by the waveform shown by the solid line in FIG. 4), and the original overvoltage suppressing effect may be canceled out, which is not preferable. Therefore,
Furthermore, in order to eliminate the drawbacks in the characteristics of the circuit shown in FIG. 3, as shown in FIG. A circuit has also been proposed in which a circuit (enclosed part) is attached to reduce the effects of various inductances, but this type of circuit has the disadvantage that the number of circuit components increases and the manufacturing cost increases.

In order to overcome all the drawbacks of the conventional circuits mentioned above, the inventors have conducted various studies and have developed a power conversion device consisting of multiple semiconductor element arms whose one end is connected to a common power supply bus and which performs switching operations with a time lag. , the semiconductor element arms connected to a common power supply bus are collectively connected to a circuit consisting of a capacitor and a resistor, and the other end of each semiconductor element connected to the common power supply bus is connected to the capacitor of the circuit through a diode, respectively. By connecting directly to the connection point with the resistor, we have found that mutual interference between semiconductor elements can be prevented and the number of component parts can be reduced, making it possible to easily achieve miniaturization and cost reduction of the overvoltage suppression circuit.

Therefore, a general object of the present invention is to effectively suppress overvoltage of each semiconductor element with a small number of components in a power conversion device configured using a large number of semiconductor elements, and to manufacture the device in a small size and at low cost. An object of the present invention is to provide an overvoltage suppression circuit for a semiconductor device.

In order to achieve the above object, in the present invention, in a power conversion device constituted by a plurality of semiconductor elements whose one end is connected to a common power supply bus, the semiconductor elements connected to the common power supply bus are collectively charged and discharged in a common manner. The semiconductor element is connected to a circuit, and the other end of each of the semiconductor elements is connected to the corresponding charging/discharging circuit via a diode.

In the above-mentioned overvoltage suppression circuit, it is preferable that the charging/discharging circuit is constituted by a series circuit of a capacitor and a resistor, and the terminals of each semiconductor element are respectively connected to the connection point of the capacitor and the resistor via a diode.

Next, embodiments of an overvoltage suppression circuit for a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 6 shows an embodiment of a transistor inverter incorporating an overvoltage suppression circuit according to the present invention, in which transistors T,, L, T3, T4 diodes D,, D2, D3 are connected to a DC power source Ed. , D4 are bridge-connected to form an inverter, and a load Z is connected to the output conductor of this inverter.
is connected. In this embodiment, in the inverter circuit, transistors T, .
For T2, a capacitor Cs and a resistor RS are connected in series between the power supply bus lines P and N, and the transistors T, ,
The terminal of T2, that is, the emitter terminal, is connected to the capacitor C.
A diode DS, , is installed at the connection point between S, and the resistor Rs, respectively.
Connect via DS2. Similarly, a capacitor CS2 and a resistor RS2 are connected in series between the power supply bus N and P for the transistors T3 and T4 whose one end, that is, the emitter terminal, is commonly connected to the other power supply bus N. The other end of the circle, that is, the collector terminal, is connected to the connection point between the capacitor Cs2 and the resistor Rs2 via diodes D and Ds4, respectively. Next, the operation of the circuit of the present invention described above will be explained with reference to FIG.

In addition, for convenience of explanation of operation, in the circuit shown in FIG.
The wiring inductance ld of the power supply bus, the wiring inductance between the transistors T, , T2, T3, and T4 connected after the bridge, ~16, and the wiring inductance of the overvoltage suppression circuit (the part surrounded by the broken line) ls, ls2 are shown hypothetically. Now, if the transistor T is in the ON state until time t, and the load current IL is flowing out in the direction of the arrow in FIG. The collector-emitter voltage vcE (FIG. 7, 1) of T, rapidly rises to the terminal voltage of capacitor CS, that is, the power supply voltage Ed.

From time t, to time t2, the collector current ic(T,) of the transistor T, decreases as shown in FIG. Power supply wiring inductance] d-capacitor C
s, - diode Ds, - diode D3 - increases through the closed circuit of the power source Ed, and its commutation is completed at time point 2. Therefore, the power supply current i(ld) (FIG. 7, 6) does not change during that period. From time t2, the charging current i(CS,) of the capacitor Cs begins to gradually decrease in accordance with the vibration frequency in the closed circuit. On the other hand, contrary to this, diode D
The current i(D3) at 3 (FIG. 7-4) begins to increase. That is, at time t2, the power supply current i(ld) (FIG. 7, 6) starts to gradually decrease in exactly the same way as the charging current i(Cs,) of the capacitor CS,. During this period, the load current I
L hardly changes depending on the load inductance. Therefore, by selecting the capacitance of the capacitor CS to an appropriate value, the power supply current i(ld) changes slowly and the collector emitter voltage vc8 of the transistor T also changes.
As shown by the broken line in FIG. 1, at time t, the change is more gradual.

Then, at time t3, the current i(D3)(
Fig. 7 4) and charging current i (CS2) of capacitor CS2
The commutation of (Fig. 7 3) is completed. In other words, the capacitor C of the energy possessed by the power supply wiring inductance ld
The transition to s, is completed at time et al. Therefore, ideally,
The collector-emitter voltage vc8(T
) changes as shown by the broken line in FIG. 7, and the voltage vcE
m is the maximum voltage applied to the transistor T. As is clear from the foregoing, in the embodiment of the present invention shown in FIG. 6, the overvoltage suppression capacitor CS, or Cs2 is each transistor T, ~
Since it is directly connected to T4, for example, when the transistor T is in an OFF state, there is almost no influence of the wiring inductances 1 and 16 between the transistors T and T4. However, even in the circuit of the present invention, since the wiring inductance IS or ls2 of the overvoltage suppression circuit cannot be completely removed, the collector of the transistor T, for example, only during the period from time to t3 as shown in FIG.・Emitter voltage vcE
The worst voltage vcBp=[Ed1iS...Katajugo] is added to (T,). However, the wiring inductance IS can be made smaller by making some changes to the circuit configuration, and the voltage relationship shown in FIG.
It is easily realized that m>vcEp, and it does not have any adverse effect in practice. According to the present invention, in a power conversion device configured of a plurality of semiconductor elements each having one end connected to a common power supply bus and performing switching operations with a time lag, overvoltage is suppressed at once for the semiconductor elements connected to the common power supply bus. By making the circuit common and connecting the uncommon terminals of the semiconductor elements to the overvoltage suppression circuit through diodes, a discharge prevention type overvoltage suppression circuit is constructed that prevents mutual interference and generates less loss. However, the number of parts can be significantly reduced compared to conventional circuits, making it possible to downsize the overall structure and reduce manufacturing costs. Furthermore, compared to conventional circuits, the circuit of the present invention can reduce the number of circuit components by about half even in the case of single-phase output, and the effect of reducing the number of circuit components becomes relatively large as the output increases to multi-phase. Become.

Although the preferred embodiments of the present invention have been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of an overvoltage suppression circuit for semiconductor elements in a conventional transistor inverter, and FIG. 2 shows the operating state of the circuit shown in FIG.
, 2 is the collector current ic(T,) of the transistor T, 3 is the charge/discharge current i(Cs,) of the capacitor Cs, and 4 is the current i(D) of the diode D3.
3) and 5 are waveform diagrams of the collector-emitter voltage vcE (T3) of the transistor L, FIG. 3 is a circuit diagram showing another overvoltage suppression circuit for semiconductor elements in a conventional transistor inverter, and FIG. The operating state of the circuit shown in the figure is shown, where 1 is the collector-emitter voltage of the transistor T, and 2 is the collector current ic(T,) of the transistor T.
, 3 is the charging/discharging current i(Ds, Cs) of the capacitor Cs,
4 is the current i (D3) of the diode D3, 5 is the collector-emitter voltage vcE (T3) of the transistor L, 6 is the power supply current i (ld), and 7 is the power supply wiring inductance l.
Each waveform diagram of the terminal voltage v(ld) of the d circuit, FIG. 5 is a circuit diagram showing still another overvoltage suppression circuit for a semiconductor device outside the conventional transistor inverter, and FIG. 6 is a circuit diagram showing a semiconductor device according to the present invention. FIG. 7 is a circuit diagram showing an embodiment of a transistor inverter incorporating an overvoltage suppression circuit, and FIG. 7 shows the operating state of the circuit shown in FIG. ), 2 is the collector current ic(T,) of the transistor T, and 3 is the capacitor C.
4 is the current i (D3) of the diode D3, 5 is the collector-emitter vcE (T3) of the transistor T3, 6 is the power supply current i (LD
) and 7 are the terminal voltage v of the power supply wiring inductance ld
(ld) is each waveform diagram. T, ~T4...Transistor, D, ~D4......
Diode, Cs,, Cs2・”...Capacitor, Rs,
,Rs2・”...discharge resistance, Ds, ~Ds4...
Diode, Ed...Power supply, Z...Load, ld...Power wiring inductance, 1, ~
16. ...Wiring inductance, lsl~ls2
．． ．． ...Wiring inductance. FIG. IFIG. 2 FIG. 3 FIG・muFIG. 5 FIG. 6 FIG. 7

Claims (1)

[Scope of Claims] 1. In a power conversion device constituted by a plurality of semiconductor elements each having one end connected to a common power supply bus, the semiconductor elements connected to the common power supply bus are collectively connected to a common charging/discharging circuit. . An overvoltage suppression circuit for a semiconductor device, wherein the other end of each of the semiconductor devices is connected to the corresponding charging/discharging circuit via a diode. 2. In the overvoltage suppression circuit according to claim 1, the charging/discharging circuit consists of a series circuit of a capacitor and a resistor, and the other end of each semiconductor element is connected to a connection point between the capacitor and the resistor via a diode. Overvoltage suppression circuit for connected semiconductor elements.