JPS6040736B2 - Surface acoustic wave tuning device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronically tuned surface acoustic wave tuning device used in television receivers, FM tuners, etc., and particularly to a tuning voltage loop circuit thereof.

Instead of tuning by directly switching the tuning circuit using a variable capacitor or a changeover switch, such a tuning device uses a variable cap tuning circuit or a voltage controlled oscillator, and tunes by applying a direct current tuning voltage. The so-called electronically tuned type is increasingly being used. However, with the method of applying a DC voltage for tuning, which is preset by the channel cutout,
In response to changes in the characteristics of the varicap and voltage controlled oscillator, the currently preset DC voltage must be adjusted to obtain the correct tuning. Therefore, instead of selecting a channel by switching a preset DC tuning voltage, a tuning device has been proposed that automatically tunes each time the channel is changed so that the correct DC tuning voltage is always set. Ta.

An example of such a channel selection device will be explained with reference to FIGS. 1 to 6.

FIG. 1 is a block diagram showing the overall configuration of the channel selection device.

In this figure, 1 is an electronically tuned tuner having a voltage-controlled local oscillator, 2 is a surface acoustic wave device (hereinafter referred to as SAW device) whose details are shown in FIG. It has an electrode 9 and two sets of output electrodes 10 and 11, forming a diamond-shaped filter. 3 is SAW element 2
4 is a waveform shaping circuit for converting the output of the detection/amplifier circuit 3 into pulses, and 5 is the desired channel for reception. 6 is an encoder for binary encoding the channel number input from switch 5, and 7 is a preset channel number encoded in binary via encoder 6. The waveform shaping circuit 4 uses that value as an initial value.
A preset down counter 8 that counts down the pulse input sent from the counter 8 starts a sweep operation when the keyboard switch 5 is operated and a channel number is selected, and stops the sweep operation when the count end signal from the counter 7 is received. This is a tuning voltage supplement circuit.

When you operate the keyboard switch 5 to select the channel number of the station you wish to receive, that channel number is encoded in binary by the encoder 6 and preset in the down counter 7, and at the same time, the tuning voltage is set by the start signal from the keyboard switch 5. The sweep circuit 8 starts a sweep operation.
As a result, the zero frequency of the local oscillator of the electronically tuned tuner 1 changes as a starting point, and the tuner 1 moves from one end of the receivable band where all the channels to be received are present to the other end. to change the tuning frequency and start line drawing tuning. At this time, the local oscillation signal from the local oscillator of the tuner 1 is also applied to the SAW element 2.

Since this element 2 already has the structure shown in FIG. However, since the output electrode 11 is provided at a farther distance from the input electrode 9 than the output electrode 10, the signal is generated later than the signal from the electrode 10.

Therefore, if the signal voltage generated by conversion at the output electrode 10 is AejWt (w = 2 f), the signal voltage appearing at the output electrode 11 can be expressed as AejW (upper-7).

Since the electrodes 10 and 11 are connected in parallel, the output voltage V of the SAW element 2 is OV=A{eM×eiW(t-
7)}, and when the amplitude is detected and amplified by the detection/amplifier circuit 3, the following output voltage Vo is obtained.

Vo=G・IVI=G・A・ノ2 (10 cosw evening 7
) Here, G: degree of increase Therefore, the output voltage Vo has a maximum frequency when f is an integer, and the interval between the frequencies at which the maximum occurs △f
When it comes to television broadcasting, the frequency of the broadcasting station is often such that it can be received every time the local oscillator frequency changes by MH2, so
If 7=1'6 msec is selected, the output voltage Vo becomes maximum at every mother MHZ as shown in FIG. 3, and each peak point can be made to correspond to each channel.

Therefore, the local oscillator of the electronic tuner 1 is controlled by the tuning voltage line drawing circuit 8, and its frequency is swept and changed from one end of the reception band to the other, thereby increasing the output obtained from the detection/amplification circuit 3. By counting the peak points, each peak point corresponds to a respective channel, so it is possible to know how many channels the signal has passed through and which channel it is tuning to.

Now, the output from this circuit 3 is converted into a pulse by a waveform shaping circuit 4, and a counter 7 is counted down using this pulse.

This counter 7 has the number of the channel to be received from the keyboard switch 5 inputted as an initial value.
It is counted down by the pulse from the detection/amplification circuit 3, and the counting ends when it is tuned to the channel to be received. Therefore, when the counter 7 generates a count end signal, this signal is applied to the tuning voltage sweep circuit 8 as a sweep operation stop signal, and the tuning voltage at that time is held. As a result, the frequency of the local oscillator of the electronic tuner 1 is maintained at the frequency at which that channel is received, and the channel selection operation is completed.

Therefore, according to this tuning device, the tuning voltage for the electronic tuner 1 is not set in advance;
Since the frequency of the local oscillator is always automatically set to the frequency required for reception of that channel, accurate tuning can be performed without adjustment.

Now, in such a tuning device, since the accuracy of the tuning voltage pull-out circuit 8 has a great influence on the accuracy of channel tuning, this circuit 8 is equipped with a circuit such as the one shown in FIG. 4 using digital technology, for example. Many things are adopted.

Therefore, to explain the tuning voltage sweep circuit shown in FIG. 4, 12 is a clock pulse generation circuit, 13 is a 12-bit counter with a carry-out output, and 14 is also a 1
2-bit counter with reset input, 15
is a 12-bit comparator that compares the data of counters 13 and 14, 16 is an RS flip-flop that is set by the carry-out output of counter 13 and reset by the match signal of comparator 15, and 17 is an analog rectangular wave output from flip-flop 16. 18 is a voltage conversion circuit that converts the output of the integration circuit 17 into an arbitrary voltage value; 19 is a voltage conversion circuit that sends the carry-out output from the counter 13 to the counter 14 before the count end signal of the counter 7 is generated; , is a gate circuit that prevents the supply of a carry-out output to the counter 14 when a count end signal is applied from the counter 7.

Note that the electronic tuner 1, keyboard switch 5, encoder 6, and counter 7 are those shown in FIG. Next, the operation of the circuit shown in FIG. 4 will be described with reference to FIG. In this figure 5, the upper numbers 0, 1, 2..., 4095
is the data value of 12-bit counter 13, and the leftmost number is 1
The data value of the 2-bit counter 14 is shown. Now, when a channel number is input to the keyboard switch 5, the counter 14 is reset and the data value becomes 0, and at the same time the gate circuit 19 is opened to allow the carry-out output from the counter 13 to pass to the counter 4.

The counter 13 counts the pulses from the clock pulse generation circuit 12, and when it finishes counting pulses from 0 to 4095, it completes one cycle of operation, and all bits become 0, generating a carry-out output. The data value for evening 14 is 0 because it has just been reset.

Therefore, when the data value of counter 3 is 0, comparator 15 generates a match signal, and RS flip-flop 1
6 is reset. Therefore, as shown in FIG. 5i, the Q output of the RS flip-flop 16 is kept at the logic ○ level. Next, when counter 3 finishes counting one cycle for the first time, its data value becomes 0 and a carry-out signal is generated at the same time, thereby causing the RS
Fritz flop 16 is set and counter 14
The data value of is 1. So, after that, counter evening 13
When the data value becomes 1, comparator 15 generates a match signal and resets RS flip-flop 16.

FIG. 5 ii shows this state. Thereafter, it operates in the same way, and every time the data value of Kawanta 13 becomes 0, the RS
Flipflop! 6 is set and counter 1
The data value of 4 increases by 1, and the RS flip-flop 16 is reset each time.

Therefore, when the RS flip-flop 16 is reset, the data value of the counter 13 shifts by 1, and its operation gradually changes from Figure 5 iii to Figure 5, and the Q output of the RS flip-flop 16 changes. A rectangular wave that becomes medium and wide is obtained sequentially. Therefore, if this Q output is converted into an analog signal by the integrator circuit 17 and then converted to a predetermined voltage by the voltage conversion circuit 18, it will be 0 at the start of the sweep, as shown in FIG.
A swept voltage is obtained that increases linearly with time.

If this voltage is applied as a tuning voltage to an electronic tuner to perform rare tuning, the counter 7 will generate a count end signal when it is tuned to a predetermined channel.
As described above, the gate circuit 19 is closed,
After that, the data value of the counter 14 will not change.
Since the data value is held, the Q output of the RS flip-flop 16 repeatedly generates a constant square wave, keeping the tuning voltage at a predetermined value and keeping the electronic tuner tuned to the selected channel. , complete the selection.
Now, in such a tuning voltage sweep circuit, in order to maintain the tuning voltage accurately and increase the frequency accuracy of the local oscillator, it is only necessary to increase the number of bits of the counters 13, 14 and the comparator 15, and analog technology The accuracy can be easily improved compared to the case where

However, on the other hand, the circuit configuration becomes complicated, so it is natural that the IC
In many cases, it is necessary to rely on MOS/IC from the viewpoint of power consumption. Therefore, the clock frequency that guarantees stable operation is currently approximately 2M.
The upper limit is HZ. Therefore, as in the example above, 1
When using a 2-bit counter, the maximum tuning voltage for selecting a channel with high tuning voltage is (zo 2 x zo 2) ÷ (2
The disadvantage is that it takes a long time to complete the channel selection, as it takes a long time (xlpi)±8 (sec).

SUMMARY OF THE INVENTION An object of the present invention is to provide a surface acoustic wave channel selection device that eliminates the drawbacks of the prior art described above and can shorten channel selection time while maintaining sufficient accuracy.

In order to achieve this object, the present invention is characterized in that the sweep speed of the tuned voltage sweep circuit can be switched at the time of channel selection.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 7 shows a tuning force sweep circuit of a channel selection device according to an embodiment of the present invention, and the same reference numerals as in FIG. 4 indicate the same or equivalent parts. Further, 20 is an all-0 detection circuit that generates one pulse every time the lower 8 bits of the counter 13 become all 0;
21 is a switch circuit that closes to the contact A side when a channel number is input to the keyboard switch 5, and closes to the contact B side when a count end signal from the counter 7 is applied, and 22 is activated by the count end signal from the counter 7. After that, the counter 14' is switched to down count by the first pulse from the waveform shaping circuit 4,
Furthermore, the sequential circuit 14' that operates to close the gate of the gate circuit 19 by the second pulse is different from the counter 14 in FIG. It is a bit up/down counter.

Next, the operation of the circuit shown in FIG. 7 will be explained.

When the keyboard switch 5 is operated and the channel number to be selected is input, the switch circuit 21 is closed to the contact A side, the counter 14' is reset, and the gate circuit 19 is opened.

Therefore, the counter 13 counts the pulses from the clock pulse generation circuit 12, and when it finishes counting one cycle from 0 to 4095 and all data values become 0, it generates a carry-out signal. Since counter 4' has been reset, when the data value of counter 3 is 0, comparator 15 generates a match signal and RS flip-flop 16 is reset. Therefore, the Q output of the RS flip-flop 16 is at the logic level.

This state is shown in FIG. 8i. This figure 8 also has the upper numbers 0, 1,..., 18... similar to the figure 5 above.
..., N, ..., 4095 is the data value of the 12-bit counter 13, and is the input channel number N'. The leftmost numerical value is the data value of the counter 14'. When the counter 13 finishes counting the first cycle and all bits become 0, a carry-out signal is generated, thereby setting the RS flip-flop 16.

The process up to this point is the same as the case shown in FIG. However, up to this point, the data value of the lower 8 bits of the counter 13 has become 18 sub-0s, so the all-0s detection circuit 20 generates a decisive pulse, and at the same time as a carry-out occurs, an additional 1-bit pulse is generated. As a result, the data value of the counter 14' becomes 17 due to these 17 pulses, and furthermore, the data value of the counter 14' becomes 17.
1 from the detection circuit 20 when counting pulses in the needle area.
Since the data value of the counter 14' becomes 18, the comparator 15 generates a match signal when the counter 13 reaches 18, and the RS flip-flop 16 is reset. Therefore, the Q output of the flip-flop becomes as shown in FIG. 8ii. Similarly, each time the data value of the counter 13 becomes 0, R
The S flip-flop 16 is reset, 17 pulses from the all-0 detection circuit 20 are input to the counter 4', and the RS flip-flop 16 is reset each time the data value becomes 35, 52, 69, . . . , 8th
As shown in FIG. iii, a rectangular wave whose medium changes greatly every cycle of the counter 13 is obtained at the Q output. Since the Q output signal that changes greatly during this pulse is supplied to the electronic tuner 1, the electronic tuner 1 performs sweep tuning at a high speed and reaches a predetermined channel in a short time. When a predetermined channel is reached, a count end signal is generated from the counter 7, as already explained. Upon generation of this count end signal, the switch circuit 21 is switched to the contact B side, the output of the all-0 detection circuit 20 is no longer applied to the counter 14', and the counter 14' is incremented only by the carry-out signal of the counter 3. Therefore, as in FIG. 4, 1 of the counter 13
The data value of the counter 14' increases by 1 every time a cycle is counted, and the tuning voltage changes slowly.

This state is shown in FIG. 8 and below. In this state, the tuning voltage changes at exactly the same speed and accuracy as in the case of FIG. 4.

Now, upon generation of the count end signal, the sequential circuit 22 is further brought into operation.

At this time, since the gate circuit 19 has not yet been closed, the data value of the counter 14' increases by 1, and the tuning voltage also increases, passing through a predetermined channel and moving to the next channel, and the waveform shaping is performed. A pulse corresponding to the next channel is received from circuit 4.

This pulse causes the sequential circuit 22 to switch the counter 14' to count down. As a result, the counter 13 becomes 1.
Each time the cycle count ends, the data value of the counter 4' is decremented by one.

The operation of the RS flip-flop 16 in this state is shown in FIG. Therefore, the tuning voltage slowly decreases, and eventually, when a pulse corresponding to the desired channel is generated again from the waveform shaping circuit 4,
Sequential circuit 22 closes gate circuit 19 and counter 14'
Keep the data value constant at the current value.

Therefore, from now on, the Q output of the RS flip-flop 16 becomes a constant rectangular wave as shown in FIG.

Figure 9 shows the state of change in the tuning voltage at this time.
The curve a shown by a solid line is for the embodiment shown in FIG. 7, and the curve shown by a broken line is for the conventional example shown in FIG. That is, according to this embodiment, the tuning voltage rapidly increases at a large rate of change as soon as the tuning starts, and when the target channel is reached, the tuning voltage gradually changes, and finally returns in the opposite direction to change the tuning voltage to the specified channel. After reaching the tuning voltage with high accuracy, it is held.

Therefore, compared to the conventional case, since the voltage accuracy is exactly the same near the tuning voltage for a predetermined channel, the tuning time can be significantly shortened without compromising frequency accuracy. This effect is especially great when a channel with a large channel number is selected.

In this embodiment, the all-0 detection circuit 20 targets the lower 8 bits of the counter 3, but it is possible to arbitrarily decide which bits to target. The sweep can be performed until a predetermined channel is reached. Next, another embodiment of the present invention is shown in FIG.

In the embodiment shown in FIG. 10, the same reference numerals as in FIG. 7 indicate the same or equivalent parts. In this embodiment, a signal for switching the switch circuit 21 from the contact A side to the B side is generated by a 1 detection circuit 23 that detects that the remaining data of the counter 7 is 1. Furthermore, the counter 4 differs from the embodiment shown in FIG. 7 in that it is a 12-bit counter similar to that shown in FIG.

The operation is the same as that shown in FIG. 7, from when the keyboard switch 5 is operated and the desired channel number is input until the tuning voltage is pulled at high speed.

Now, in this way, the tuning voltage is swept at high speed, and when it reaches one channel before the desired channel, the counter 7
The data becomes 1.

Therefore, the switch circuit 21 is closed to the contact B side by the 1 detection circuit 23.

As a result, as in the case of FIG. 7, the sweep of the tuning voltage is switched to a low speed, and when the target channel is reached, the counter 7 finally generates a count end signal, so the gate circuit 19 is closed and the tuning voltage is held constant to complete the channel selection. This change in tuning voltage is shown in FIG.

The curve a shown by a solid line is for this embodiment, and the curve b shown by a broken line is for the conventional example shown in FIG. In addition, in this embodiment, when selecting the first channel, bridge pulling is performed at a low speed after the tuning start interval, but since the tuning voltage is reached immediately, it does not take a long time. ,
Almost no problem. In addition, in this embodiment, the Nishikihiki is switched from high speed to low speed when the channel one channel before the target channel is reached, but it can be switched at any channel before that. Of course, this is a good thing.

As described above, according to the present invention, channel selection can be performed in an extremely short time compared to conventional circuits, and there is no fear that the tuning accuracy will deteriorate at that time. Comparing this with an actual example, when the conventional system uses a clock frequency of 2MH2, it takes a maximum of about 8 seconds to select a station, whereas the present invention uses the same clock frequency. Even if the frequency is used, it is possible to tune within one second at maximum, and the tuning accuracy can be maintained at the same level or higher.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the entire surface acoustic wave tuning device, Fig. 2 is a configuration diagram of a surface acoustic wave element, Fig. 3 is a characteristic diagram of a comb-shaped filter obtained by the surface acoustic wave element, and Fig. 4 is a conventional one. Block diagram of tuned voltage sweep circuit, Figures 5 and 6
7 is a block diagram of a tuned voltage sweep circuit according to an embodiment of the present invention, FIGS. 8 and 9 are illustrations of its operation, and FIG. 10 is an illustration of another embodiment of the present invention. FIG. 11 is a block diagram of a tuning voltage sweep circuit according to an example, and is an explanatory diagram of its operation. 1...Electronic tuner, 2...Surface acoustic wave element, 3.
...Detection/intensification circuit, 4...Waveform shaping circuit,
5...Keyboard switch, 6...Encoder, 7. ．．
・．． ．．・Counter, 8... Tuned voltage sweep circuit,
12.. ．． ...Clock pulse generation circuit, 13, 14
, 14', 14a, 14b...Power loader, 15...Comparator, 16...RS flip-flop, 1
7...Integrator circuit, 19...Gate circuit, 20...All 0 detection circuit, 21...
- Switch circuit, 23...1 detection circuit. 2 figures, 3 figures, 4 figures, 5 figures, 5 figures, S figures, 7 figures, A figures, 0 figures, 1 figure.

Claims (1)

[Claims] 1. An electronic tuner having a voltage-controlled local oscillator;
A tuned voltage sweep circuit for sweeping the oscillation frequency of the local oscillator, a surface acoustic wave comb filter that takes the output signal of the local oscillator as an input signal, and an output signal of the surface acoustic wave comb filter are input. A detection circuit that detects a signal, a waveform shaping circuit that receives the output signal of the detection circuit and shapes the input signal, a keyboard switch, an encoder that encodes the output signal of the keyboard switch, and an output signal of the encoder. and a first counter that counts the output signal of the waveform shaping circuit using the preset value as an initial value, and when the first counter finishes counting, the tuning voltage sweep circuit performs a sweep operation. In a tuning device in which a television signal is tuned when the television signal is stopped, a tuned voltage sweep circuit includes: a) a clock generation circuit; b) a second counter that counts the output signal of the clock generation circuit; and c) a second counter. a first detection circuit that detects a predetermined count value of d, a switch that selects one of them by using the output signal of the first detection circuit and the carry-out output of the second counter as input signals; The output signal and the counting end signal of the first counter are input, and before the counting end signal is input, the output signal of the switch is derived, and after the counting end signal is input, the output signal of the switch is derived. A gate circuit that prohibits derivation of the signal, f a third counter that counts the output signal of the gate circuit, g a comparator that compares the output signals of the second and third counters, and h a carry-out output of the second counter. a flip-flop that is thus set and reset by the output signal of the comparator; i an integrating circuit that integrates the output signal of the flip-flop; j a voltage conversion circuit that converts the output signal of the integrating circuit into voltage; and k a first counter. and a second detection circuit that detects that the voltage has reached a predetermined value, and the switch is controlled by the output signal of the second detection circuit to change the sweep speed of the tuning voltage. surface acoustic wave tuning device.