JPS6040738B2 - switching circuit - Google Patents
switching circuitInfo
- Publication number
- JPS6040738B2 JPS6040738B2 JP54067880A JP6788079A JPS6040738B2 JP S6040738 B2 JPS6040738 B2 JP S6040738B2 JP 54067880 A JP54067880 A JP 54067880A JP 6788079 A JP6788079 A JP 6788079A JP S6040738 B2 JPS6040738 B2 JP S6040738B2
- Authority
- JP
- Japan
- Prior art keywords
- contact
- relay
- thyristor
- turns
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 3
- SEPPVOUBHWNCAW-FNORWQNLSA-N (E)-4-oxonon-2-enal Chemical compound CCCCCC(=O)\C=C\C=O SEPPVOUBHWNCAW-FNORWQNLSA-N 0.000 description 1
- LLBZPESJRQGYMB-UHFFFAOYSA-N 4-one Natural products O1C(C(=O)CC)CC(C)C11C2(C)CCC(C3(C)C(C(C)(CO)C(OC4C(C(O)C(O)C(COC5C(C(O)C(O)CO5)OC5C(C(OC6C(C(O)C(O)C(CO)O6)O)C(O)C(CO)O5)OC5C(C(O)C(O)C(C)O5)O)O4)O)CC3)CC3)=C3C2(C)CC1 LLBZPESJRQGYMB-UHFFFAOYSA-N 0.000 description 1
- 235000011468 Albizia julibrissin Nutrition 0.000 description 1
- 240000007185 Albizia julibrissin Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/13—Modifications for switching at zero crossing
- H03K17/136—Modifications for switching at zero crossing in thyristor switches
Landscapes
- Electronic Switches (AREA)
- Thyristor Switches And Gates (AREA)
- Relay Circuits (AREA)
Description
【発明の詳細な説明】
本発明は耐アーク性よりSCR、トライアツク等の半導
体スイッチング素子(以下3端子サィリスタという)に
よる無接点で電路をしや断するスイッチング回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching circuit that disconnects an electric path without contact using a semiconductor switching element (hereinafter referred to as a three-terminal thyristor) such as an SCR or a triac due to arc resistance.
この種3端子サィリスタを用いて電路をしや断するもの
は、該サィリスタの前後に動作時点の異なる接点を各々
配し、先に動作した薮点にて該サィリスタをトリガさせ
、続いて多少遅れて次の接点をオンさせており、オフ時
はその逆として耐アーク性能を考慮している。This kind of 3-terminal thyristor is used to break the electric circuit by placing contacts with different operating times before and after the thyristor, and triggering the thyristor at the first operating point, followed by a slight delay. The next contact is turned on, and vice versa when it is turned off, considering arc resistance performance.
そして、電流変化率を低くしノイズの低減を図っている
。その従来例として第1図に示すものがある。The current change rate is lowered to reduce noise. A conventional example of this is shown in FIG.
これについて説明すると、1は入力側端子で、信号によ
って動作するりレー2を接続している。而してこのリレ
ー2は動作時点の異なる3つの接点2a,2b,2cを
有する。3は交流電源、4は誘導性負荷、5は3端子サ
ィリスタで、前記電源3及び負荷4と出力側端子6を介
して端子T1,TOが接続されている。To explain this, reference numeral 1 denotes an input side terminal to which a relay 2 which operates according to a signal is connected. This relay 2 has three contacts 2a, 2b, and 2c that operate at different times. 3 is an AC power supply, 4 is an inductive load, and 5 is a three-terminal thyristor, the terminals T1 and TO are connected to the power supply 3 and load 4 via an output terminal 6.
而してこの3端子サィリスタ5のゲート端子Gに前記リ
レー2の最初の段に動作する上段接点2aが接続され、
この穣点2aがオンすればゲート端子Gはトリガされ、
両端子T1,TO‘こ電圧が印加され、サィリスタ5は
オンされる、このオン状態は一定電流以下になるまで維
持される。7はゼロクロスで、上段接点2aに接続され
電流波形の零近僕でオン、オフする。The upper stage contact 2a, which operates in the first stage of the relay 2, is connected to the gate terminal G of this three-terminal thyristor 5,
When this cross point 2a turns on, the gate terminal G is triggered,
A voltage is applied to both terminals T1 and TO', and the thyristor 5 is turned on. This on state is maintained until the current drops below a certain level. 7 is a zero cross, which is connected to the upper contact 2a and turns on and off when the current waveform approaches zero.
この上段接点2aがオンした後半サイクル以上の遅れ時
間をもって中段接点2bがオンされるよう抵抗8と共に
並列接続されている。この抵抗8はサィリスタ5への正
常なトリガと、接点2bの開閉アークの眼流と、更にサ
ィリスタ5がオンした後はこ)を流れるためのものであ
る。更に最終段でオンする後段接点2cはサィリスタ5
と並列となっている。オフに際しては接点2a,2b,
2cは逆動作順序となる。次に本発明スイッチング回路
の動作を第2図と共に説明すると、入力側端子1に入力
信号が入るとIJレー2が動作する。The middle contact 2b is connected in parallel with the resistor 8 so that the middle contact 2b is turned on with a delay time longer than the second half cycle when the upper contact 2a is turned on. This resistor 8 is used for normal triggering of the thyristor 5, for the opening/closing arc of the contact 2b, and for the flow after the thyristor 5 is turned on. Further, the second stage contact 2c that turns on at the final stage is the thyristor 5.
It is paralleled with. When turning off, contacts 2a, 2b,
2c is the reverse operation order. Next, the operation of the switching circuit of the present invention will be explained with reference to FIG. 2. When an input signal is input to the input terminal 1, the IJ relay 2 operates.
このリレー2の動作によて上段接点2aが入る。而して
ゼロクロス6により第2図の負荷電流の如く零近傍より
サィIJスタ5はトリガされ電流が流れる。この上段接
点2aに半サイクル以上遅れて中段接点2bがオンし、
上段接点2aのゼロクロス6と関係なく電源3一負荷4
一抵抗8一中段接点2b−ゲート端子Gとサィリスタ5
は常に付勢されるのである。最終の後段接点2cは更に
遅れてオンされる。従って突入電流のア÷クはこの後段
接点2cでは発生しないのである。従って電源3一負荷
4−後段一点2cと回路が出釆、負荷は運転される。続
いて負荷4を断つ場合は入力信号の消滅によってリレー
2が復帰し、後段接点2cを先ずオフにする。This operation of relay 2 causes upper contact 2a to close. Then, the zero cross 6 triggers the IJ star 5 from near zero, as shown in FIG. 2, and the current flows. The middle contact 2b turns on more than half a cycle after the upper contact 2a,
Power supply 3 - load 4 regardless of zero cross 6 of upper contact 2a
- Resistor 8 - Middle contact 2b - Gate terminal G and thyristor 5
is always energized. The final post-stage contact 2c is turned on with a further delay. Therefore, the inrush current does not occur at the subsequent contact 2c. Therefore, the circuit of power source 3 - load 4 - one point 2c of the latter stage is activated, and the load is operated. When the load 4 is subsequently cut off, the relay 2 returns to normal operation as the input signal disappears, and the subsequent contact 2c is first turned off.
この場合、サィリスタ5の並列回路によってァークは飛
ばないのである。この後中段接点2bがオフとなりこの
接点2bとサィリス夕5との関係は解放されるが、ゼロ
クロス6と上段接点2aとでサィリスタ5は未だトリガ
拘束下にある。後、このゼロクロス6の零近僕動作でオ
フとなりサィリスタ5もオフとなって負荷4を断つ。尚
、第2図は電源、入力信号、各接点2a,2b,2c、
ゼロクロス6の動作時間を示す。この中段接点2bはゼ
ロクロス6の隣点と後段接点2cとの動作時点とが重な
ることによって接点2cにて直接回路しや断することを
防止するものである。このようにして電流変化率を低く
し、ノイズの低減を図ることができるが、時間差を有す
る接点を少なくとも3個以上必要とするため、リレー接
点の調整が難しいという欠点があった。In this case, the arc does not fly due to the parallel circuit of the thyristor 5. Thereafter, the middle contact 2b is turned off and the relationship between the contact 2b and the thyristor 5 is released, but the thyristor 5 is still under trigger restraint due to the zero cross 6 and the upper contact 2a. After that, the near-zero operation of this zero cross 6 turns off, and the thyristor 5 also turns off, cutting off the load 4. In addition, Fig. 2 shows the power supply, input signal, each contact 2a, 2b, 2c,
The operation time of zero cross 6 is shown. This middle stage contact 2b prevents the circuit from being directly disconnected at the contact 2c due to the timing of operation of the point adjacent to the zero cross 6 and the second stage contact 2c overlapping. In this way, the rate of change in current can be lowered and noise can be reduced; however, since at least three contacts with time differences are required, it is difficult to adjust the relay contacts.
又、誤動作を生ずる可能性もあった。そこで、本発明は
このような従来の欠点を除去した新規なスイッチング回
路を提供することを目的とする。以下、第3図以降をも
つて本発明の一実施例を説明するが、第1図の従釆回路
も同一部分は同一符号を付しその説明を省略する。Additionally, there was a possibility that malfunctions would occur. Therefore, an object of the present invention is to provide a novel switching circuit that eliminates such conventional drawbacks. Hereinafter, one embodiment of the present invention will be described with reference to FIG. 3 and subsequent figures, but the same parts in the slave circuit of FIG.
9は発光ダイオードで前記リレー2と直列に接続されて
いる。A light emitting diode 9 is connected in series with the relay 2.
10‘ま発光ダイオード9の照射光に応動して作動する
ゼロクロストリガ回路、11は夫合発光ダイオード9、
リレー2と並列に接続されたダイオードであり発光ダイ
オード9の保護用である。10' is a zero cross trigger circuit that operates in response to the light irradiated by the light emitting diode 9; 11 is a light emitting diode 9;
This diode is connected in parallel with the relay 2 and is used to protect the light emitting diode 9.
2xは前段接点でありリレー2への励磁開始から半サイ
クル以上遅れて作動する。2x is a front-stage contact, which operates with a delay of more than half a cycle from the start of excitation to relay 2.
2yは後段接点で前段接点2×より若干遅れて閉成し開
成は早い。2y is a rear contact, which closes slightly later than the front contact 2x and opens earlier.
次にこのような本発明の構成による動作を第4図と共に
説明すると、入力側端子1に入力信号が入ると発光ダイ
オード9が発光しゼロクロストリガ回路10が応動し負
荷電流の零近傍でトリガパルスipが発生しサィリスタ
5がトリガされオンとなる。Next, the operation of the configuration of the present invention will be explained with reference to FIG. 4. When an input signal is input to the input terminal 1, the light emitting diode 9 emits light, the zero cross trigger circuit 10 responds, and a trigger pulse is generated when the load current is near zero. ip is generated and the thyristor 5 is triggered and turned on.
同時にリレー2も励磁されるが前段接点2xはトIJガ
時点よりも若干遅れてオンし以後サィリス5をトリガす
る。更に遅れて後段接点2yがオンする。そのため突入
電流のァークはこの後段接点2yでは発生せず電源3−
負荷4−接点2yと閉回路が形成され負荷は運転される
。その後、負荷4を断つ場合は入力信号の消滅によって
なされる。At the same time, the relay 2 is also energized, but the front contact 2x turns on a little later than when the IJ is triggered, and thereafter triggers the siris 5. After a further delay, the latter contact 2y turns on. Therefore, the arc of inrush current is not generated at the subsequent contact 2y, and the power supply 3-
A closed circuit is formed between the load 4 and the contact 2y, and the load is operated. Thereafter, when the load 4 is cut off, the input signal disappears.
これは発光ダイオード9が発光せず、リレー2も励磁さ
れないためまず後段接点2yがオフし次に前段接点2×
がオフする。そのためこれら接点2×,2yにはァーク
が発生せず、そのオフの後に負荷電流の零近傍でサィリ
スタ5がオフとなり負荷を断つ。尚、入力端子1に誤っ
て逆方向に入力信号が印放されたときはダイオード11
の短絡によって発光ダイオード9の破損を防止できる。This is because the light emitting diode 9 does not emit light and the relay 2 is not excited, so the rear contact 2y is turned off first, and then the front contact 2x is turned off.
turns off. Therefore, no arc is generated at these contacts 2x and 2y, and after the contacts 2x and 2y are turned off, the thyristor 5 is turned off when the load current is near zero, cutting off the load. Note that if an input signal is accidentally released to input terminal 1 in the opposite direction, diode 11
Damage to the light emitting diode 9 due to short circuit can be prevented.
即ち、上述した本発明によれば負荷電流を零近僕でオン
,オフ動作させる場合、リレーの接点は2個のみでよい
。That is, according to the present invention described above, when the load current is turned on and off near zero, only two relay contacts are required.
そしてサイリス夕をまずオンさせるゼロクロストリガ回
路は光結合されているため接点を必要とせず応動に全く
遅れがなくリレーと接点との間に遅延手段を用いなくて
も接点の動作に先立って作動し円滑な作動を行なうこと
ができる全体的に調整が容易で動作も確実なスイッチン
グ回路を提供できる。The zero-cross trigger circuit that turns on the thyristor first is optically coupled, so it does not require any contacts and there is no delay in response, and it can be activated prior to the operation of the contacts without using any delay means between the relay and the contacts. It is possible to provide a switching circuit that can operate smoothly, is easily adjustable overall, and has reliable operation.
第1図は従来のスイッチング回路の回路図、第2図はそ
の動作を示す波形図、第3図は本発明の一実施例を示す
回路図、第4図はその動作を示す波形図である。
1・・・・・・入力端子、2・・・・・・リレー、3・
・・・・・交流電源、4・・・・・・負荷、5・…・・
サィリスタ、9・・・・・・発光ダイオード、10・・
・・・・ゼロクロストリガ回路、2x…・・・前段穣点
、2y・・・・・・後段接点。
そ’IQナ21幻
才21幻
矛4銭Fig. 1 is a circuit diagram of a conventional switching circuit, Fig. 2 is a waveform diagram showing its operation, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a waveform diagram showing its operation. . 1...Input terminal, 2...Relay, 3.
...AC power supply, 4...Load, 5...
Thyristor, 9... Light emitting diode, 10...
...Zero cross trigger circuit, 2x... front stage contact, 2y... rear stage contact. So'IQ na 21 phantom talent 21 phantom spear 4 sen
Claims (1)
スタと直列に接続された負荷と、入力信号より半サイク
ル以上遅れてオン動作する前記3端子サイリスタのゲー
ト端子に接続されたリレーの前段接点と、該リレーの前
段接点の動作に先がけて前記3端子サイリスタを零近傍
でオンさせる入力側と光結合されたゼロクロストリガ回
路と、前記リレーの前段接点より更に遅れてオン動作し
、且つ前記入力信号がオフとなつたとき前記リレーの前
段接点より先にオフ動作する前記3端子サイリスタに並
列に接続された前記リレーの後段接点とよりなるスイツ
チング回路。1. a 3-terminal thyristor, a load connected in series with the 3-terminal thyristor to an AC power supply, and a front-stage contact of a relay connected to the gate terminal of the 3-terminal thyristor that turns on with a delay of more than half a cycle from an input signal; a zero cross trigger circuit optically coupled to the input side that turns on the three-terminal thyristor near zero prior to the operation of the front contact of the relay; A switching circuit comprising a rear contact of the relay connected in parallel to the three-terminal thyristor, which turns off before a front contact of the relay when turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54067880A JPS6040738B2 (en) | 1979-05-31 | 1979-05-31 | switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54067880A JPS6040738B2 (en) | 1979-05-31 | 1979-05-31 | switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55159631A JPS55159631A (en) | 1980-12-11 |
| JPS6040738B2 true JPS6040738B2 (en) | 1985-09-12 |
Family
ID=13357655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54067880A Expired JPS6040738B2 (en) | 1979-05-31 | 1979-05-31 | switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6040738B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4356525A (en) * | 1981-01-05 | 1982-10-26 | General Electric Company | Method and circuit for controlling a hybrid contactor |
-
1979
- 1979-05-31 JP JP54067880A patent/JPS6040738B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55159631A (en) | 1980-12-11 |
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