JPS6041509B2 - AFC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal AFC circuit for a television receiver, and more particularly to an improvement of the AFC circuit in which the control voltage for the horizontal oscillation circuit is limited by the limiter action of a limiter circuit.

FIG. 1 is a horizontal deflection system block diagram including an AFC circuit.

In the figure, 1 is an AFC circuit, 2 is an input terminal, 4 is a horizontal oscillation circuit, 5 is a drive circuit, 6 is a horizontal output circuit, and 7 is a flyback transformer. The output signal of the horizontal oscillation circuit 6 and the synchronously separated horizontal synchronization signal S are used as comparison signals.
(frequency t days) is supplied to the AFC circuit 1 and compared. In this case, when the frequency tH of the input signal S, changes, the control voltage ev also changes, and the oscillation frequency of the horizontal oscillation circuit 4 is adjusted to the frequency fH by this control voltage ev. The output of the oscillation circuit 4 passes through the drive circuit 5 to switch the horizontal output transistor.

By this switching, the horizontal output circuit 6 generates a pulse, which is step-up rectified by the flyback transformer 7 and the high voltage is supplied to the anode of the cathode ray tube. However, if the horizontal synchronizing frequency fH deviates low for some reason (such as during fast forwarding in a video tape recorder) and this fH is within the holding range of the AFC circuit 1, the pulse wave generated from the horizontal output circuit 6 The high value increases, and the anode voltage of the cathode ray tube also increases.

In such a state, not only the cathode ray tube but also the high voltage generating parts are susceptible to dielectric breakdown, which is extremely dangerous. That is, if the holding range of AFC times*1 is wide, the above-mentioned abnormal high pressure may occur, which may cause a failure.

In order to solve this problem, as shown in Figure 1,
The control voltage ev, which is the output of the AFC circuit 1, is clamped by a limiter circuit 8 so that it does not go below a certain voltage e (and in the case of the dotted line, it goes up to e).

However, as shown in S in FIG. 2 and as is well known, in the horizontal synchronization signal during the vertical synchronization signal period Vs,
Since it is larger than other periods, the control voltage ev, which is the output of the AFC circuit 1, is as shown by the curve ev in FIG.
There is a large ripple near the vertical synchronization signal period Vs. This ripple is the clamp voltage e of the limiter circuit 8,
, the video signal period after the vertical female line period Vr (
The influence of this ripple continues until t) in FIG.

This causes the vertical lines at the top of the reception screen to bend or sway, resulting in an unsightly screen. Note that the dotted line in FIG. 2 ev is the control voltage waveform when no clamping operation is performed, and in this case, the above-mentioned drawback does not occur. The present invention prevents the received image from bending or shaking at the top of the screen, and also makes it possible to limit the control voltage during changes.
It provides an FC circuit.

In order to achieve the above object, in the present invention, from almost the start of the vertical synchronizing signal period, so that the clamping effect does not occur even if the ripple of the control voltage exceeds the clamp voltage value near the vertical synchronizing signal period, At least, after the control voltage exceeds the clamp voltage, until the time when the control voltage returns to the clamp voltage again, the limiter operation is relaxed by increasing the clamp voltage, or the limiter circuit itself is turned off. However, in other periods, the desired Clasp voltage is maintained.

The AFC circuit according to the present invention will be explained below with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.

Since the same parts as in FIG. 1 are indicated using the same reference numerals, the explanation of these parts will be omitted. In order to solve the above problem, this embodiment is characterized by the use of a limiter circuit as described below.

In order to operate the transistor 9 with direct current, resistors 10 and 11 are connected.
The base of the transistor 9 is connected to the connection point of the transistor 9, and the collector of the transistor 9 is connected to a voltage of 10B.
Further, its emitter is connected to ground via a resistor 13 and to a diode 14. The cathode of the diode 14 is connected to the output side of the AFC circuit 1. The connection rule for resistors 1 and 12 is that the collector of transistor 5 is connected, and its emitter is connected to ground.

The base of the transistor 15 is supplied with a vertical erase pulse 1.
6 is on offer. A vertical blanking pulse 16, which is typically generated in the vertical output circuit, is applied to the video circuit to
Although used to perform vertical line cancellation, this pulse can also be used as pulse 16 applied to the base of transistor 15. The operation of this embodiment will be explained in detail below.

When the horizontal synchronizing signal S has a normal frequency fH=fo and the vertical female erase pulse 16 is not applied to the base of the transistor 15, the bias relationship of this circuit is as follows. Control voltage ev > limiter circuit operating point voltage e, e・
=ee-Vゞ-R. ≦Konguro 33V8-V Group-V'...
.

1 However, ee...emitter voltage of transistor 9, Vf
...Forward voltage drop of diode 14, R. ... value of resistor 10, R2... value of resistor 11, R3... value of resistor 12, V8... 10B voltage, V88... base emitter voltage of transistor 9 is fo As the voltage becomes lower, the control voltage ev also becomes lower.

When the control voltage ev attempts to become lower than the clamp voltage e, the diode 14 is turned on, so that the control voltage ev is held at the value of e. Further, when the vertical female erase pulse 16 is applied in the state of fH=fo, the transistor 15 is turned on, so the bias relationship is as follows.

ev>e, > limiter circuit operating point light pressure e,'e. '=Takashi e-Vf=R; ≦Electric VB-V Thin-Vr...■However, e
'e=emitter voltage of transistor 9 As can be seen from the above equation {1', You can choose a lower value than that. I at this time
If the J-mitter operating point e' is selected at a level that does not clip the ripple of the control voltage ev near the vertical synchronization signal (or reduces the degree of clipping), the upper part of the screen will not curve. , there will be no more shaking. As is clear, it is possible to choose e' in this way. FIG. 4 shows a second embodiment of the invention.

The difference from the first embodiment shown in FIG. 3 is that the transistor 9 is configured to turn off when a vertical female erase pulse is applied. This will be explained in detail below. The vertical wire erase pulse 16 is applied to the base of a transistor 17 whose emitter is connected to ground and whose collector is connected through a resistor 18 to the 10B power supply. The base of a transistor 19 is connected to the connection point between the collector of the transistor 17 and the resistor 18, the emitter of the transistor is connected to ground, and the collector is connected to the resistor 20, 2.
Connected to 10B power supply through 1. The resistors 20, 21
The connection point of the transistor 22 is connected to the base of the transistor 22.

The emitter of transistor 22 is connected to the 10B power supply, and its collector is connected to ground through resistors 23 and 24. The base of the transistor 9 is connected to the connection point between the resistors 23 and 24. Other configurations and connections are the same as in FIG. 3. When the vertical line erase pulse 16 is not applied to the transistor 17, the transistor 17 is off, so the transistor 19 is turned on through the resistor 18, and thereby the transistor 22 is also turned on.

As a result of the above, the base of the transistor 9 is connected to the resistors 23 and 2.
A voltage divided by 4 will be applied. At this time, it is possible to select the values of the resistors 23 and 24 so that the emitter potential of the transistor 9 is the same as in the first embodiment. On the other hand, when the vertical line erase pulse 16 is applied to the base of the transistor 7, the transistor 17 is turned on, the transistor 19 is turned off, and the transistor 22 is also turned off. As a result, the base voltage of the transistor 9 becomes 0v, so the transistor 9 can be turned off.
Therefore, the emitter potential of the transistor 9 - that is, the anode potential of the diode 14 becomes 0, and the limiter operation is prohibited. In the above, only the case where the control voltage ev decreases has been illustrated and described, but FIG. 5 shows an embodiment where the control voltage increases.

In the figure, the vertical female erase pulse 16 is applied to the transistor 2.
5, transistor 25 is on,
Transistor 26 is turned off. As a result, the base voltage of transistor 9 becomes high, and its emitter potential, that is, the cathode potential of diode 14 becomes high. In other periods (periods in which there is no vertical female erase pulse 16), the transistor 25 is off and the transistor 26 is on, so that the base-to-fin level of the transistor 9 is lowered. Therefore, the cathode potential of diode 14 becomes low. In this way, the cathode position of the diode 14, that is, the clamp pressure of the limiter circuit can be switched. In each of the above-described embodiments, a vertical female erase pulse is used, but it is clear that a pulse generated by a vertical oscillation circuit may be used instead.

As is clear from the above description, according to the present invention, it is possible to eliminate the drawbacks of conventional limiter circuits, prevent bending and shaking of the upper part of the received image, and limit the change in control fin pressure. . Furthermore, as can be seen from FIGS. 3 to 5, each embodiment of the present invention consists only of resistors, transistors, and diodes, and does not include capacitors.
It is suitable for IC implementation.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a horizontal deflection circuit including a conventional limiter circuit, Fig. 2 is a control voltage waveform diagram and a diagram illustrating the relationship between the limiter circuit operating point and the control voltage, and Figs. FIG. 5 is a circuit diagram showing an embodiment of the present invention. 1...AFC circuit, 4...Horizontal oscillation circuit, 5...Drive circuit, 6...Horizontal output circuit, 8...Limiter circuit. Dimensions 1 figure 2 figures 3 figures 7 mu garden figures 5 figures

Claims (1)

[Claims] 1. A reference signal and a comparison signal are supplied to an AFC circuit to obtain a desired horizontal oscillation circuit control voltage, and the range of change in the control voltage is limited by a limiter action of a limiter circuit. In the AFC circuit, the limiter circuit of the limiter circuit operates at least until the control voltage returns to the clamp voltage after the control voltage exceeds the clamp voltage of the limiter circuit. An AFC circuit characterized in that it is configured to ease operation. 2. The limiter operation is prohibited from approximately the start of the vertical synchronization signal period until at least the time when the control voltage returns to the clamp voltage after exceeding the clamp voltage of the limiter circuit. The AFC circuit according to claim 1, characterized in that: