JPS6041777B2 - Program processing monitoring method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a CPU program processing monitoring method.

In a real-time control system with multi-parallel processing, the program may run out of control due to unpredictable causes, enter into a continuous loop state and do not perform normal control operations, and in the worst case, the controlled system may be destroyed due to malfunction. It could happen. In a real-time system, it is necessary to constantly monitor whether normal processing operations are being performed, and to operate a fail-safe device in the event of an abnormality.
Conventional monitoring method that sets up a monitoring timer that times out in a slightly longer time than the processing time of the main loop of the program, issues a timer reset command for each loop during the program, and when the timer times out, it determines that there is an abnormality and issues an alarm. There is. With this method, if the clock commonly used by the CPU and its peripherals fails, the abnormality in program processing cannot be detected, and if separate clocks are used for each, both clocks must be normal. We need another means to confirm this. The present invention aims to provide a program processing monitoring method that eliminates such drawbacks, and uses the clock of a peripheral device to advance the counts of a first monitoring timer and a second monitoring timer, and also uses the same clock to advance a third monitoring timer. In addition, in the middle of the program, insert an instruction to reset the first watchdog timer, a reset instruction to reset the second watchdog timer, and an instruction to advance the count of the third watchdog timer. It is characterized by mutual monitoring with the clock.

When a program is run using this method, if a normal loop is running at a normal time, the first and second watchdog timers will continue to count according to the clock, but for a shorter time than the time it takes to count up. A monitoring timer reset instruction is executed to clear the count.

Further, the third monitoring timer is counted up by a command from the CPU, but is cleared by the peripheral device clock and does not count up. Peripheral clock is normal and CPU
If the timer goes through an abnormal loop, the first or second timer reset command is not issued even after a certain period of time, so the first or second monitoring timer times out and issues a system alarm. . When the peripheral device clock is abnormal and the CPU is operating normally, the third monitoring timer advances the count according to the CPU's command, and when the timer expires, a system alarm is issued. This will be explained in detail below using the drawings.

Figure 1 shows the conventional system, 13 and 17 are timers, 12 and 16
110 and 111 are clock input terminals, 14 and 18 are count-up output terminals, and 113 is an OR circuit. When a clock is applied to the 19 terminal, 13,1
7 advances the count.

If a reset signal is periodically applied to terminals 11 and 15, no count-up output will be output to terminals 14 and 18, and no alarm will be output to terminal 112. When the periodic reset signal currently applied to the terminal 11 stops, the timer 13 becomes time-up and a time-up output is output to the terminal 14. The OR circuit 113 operates and outputs an alarm to the terminal 112.

On the other hand, the same holds true even if the reset signal applied to the terminal 15 is stopped. However, in the conventional system, if the clock given to 19 stops, the monitoring function cannot be performed. FIG. 2 shows the method according to the present invention, 23, 27, 217 are timers, 22, 2
6, 214 are reset input terminals, 210, 211, 21
6 is a clock input terminal, 213 is an OR circuit, and 219 is a differential circuit.

The clock input to the terminal 29 is the clock input terminal 21
0 and 211, the timers 23 and 27 advance the count, and due to the count reset signal periodically input from 21 and 25, the timers 23 and 27 do not count up in the same way as explained in Fig. 1. . On the other hand, the timer 217 advances the count by the timer advance instruction input from 215, but the clock input from 29 causes the timer 217 to continue counting.
A reset command is input to 14, and no count-up output is output to 218. If the reset command does not come regularly to the terminal 21 or 25, the timer 23 or 27 times out and an alarm is output to the terminal 212, as in the case of FIG. On the other hand, if the clock at terminal 29 is cut off, timers 23 and 27 will stop and no time-up output will be output to 24 and 28, but each time a timer advance command is issued to 215, the timer count will advance and count up. A count up output is output at 218, an OR is taken by the OR circuit at 213, and an alarm output is output at 212. The 219 employs a differentiating circuit so that it operates even when the clock has a fault on the reset side polarity.

FIG. 3 shows a flowchart of the program of this system.

It is possible to set multiple timers whose counts are advanced by a clock and reset by a command to precisely monitor the progress of the program. It is possible to create a highly accurate system by creating a clock for the peripheral devices of this system that is different from the clock for operating the own system CPU.
If there is sufficient operating time for the fail-safe device, the system can be simplified by collecting pulses transmitted from the companion device or 50 Hz/60 Hz from the commercial power source as a clock. In addition, when performing highly accurate loop monitoring, it is possible to increase the number of timers corresponding to the first and second monitoring timers and monitor each part of the loop. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a conventional monitoring system, FIG. 2 shows an embodiment according to the present invention, and FIG. 3 shows a flowchart of a program as a system.

23, 27, 217 are timers, 22, 26, 214 are reset input terminals, 210, 211, 216 are clock input terminals, 213 is an OR circuit, and 219 is a differential circuit.

Claims (1)

[Claims] 1. Advance the count of the first supervisory timer and the second supervisory timer using the clock for the peripheral device, reset the third supervisory timer using the clock, and set the first supervisory timer in the middle of the CPU program. , a reset instruction for the second monitoring timer, and an instruction to advance the count of the third monitoring timer, and the count-up signals of the first, second, and third monitoring timers are used as an alarm. program processing monitoring method.