JPS6041858B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6041858B2 JPS6041858B2 JP55008532A JP853280A JPS6041858B2 JP S6041858 B2 JPS6041858 B2 JP S6041858B2 JP 55008532 A JP55008532 A JP 55008532A JP 853280 A JP853280 A JP 853280A JP S6041858 B2 JPS6041858 B2 JP S6041858B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- circuit board
- semiconductor device
- chip
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/15—Containers comprising an insulating or insulated base
- H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特にチップキャリヤー型
半導体装置用容器の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to an improvement in a container for a chip carrier type semiconductor device.
従来チップキャリヤー型半導体装置用容器（以後パッ
ケージと呼ぶ）はパッケージからリードを除去し、回路
基板又はマザーボードに対してパッケージが占める庄面
積を減少し実装密度を向上させることが目的であつた。Conventional chip carrier type semiconductor device containers (hereinafter referred to as packages) have been designed to remove leads from the package, reduce the area occupied by the package relative to the circuit board or motherboard, and improve packaging density.
しかし、ここでこのパッケージと回路基板との接合方法
における接合作業方法及び接合強度、熱放散、回路基板
の材質などについて問題となつていた。これらの問題点
について、従来のパッケージ構造について第１図の斜射
図、第２図の断面図、第３図の回路基板に接合した状態
の断面図を用いて説明する。パッケージは、セラミック
基板１ａに半導体素子２ａ（以後１、Ｃチップと呼ぶ）
を接着するチップ搭載部３ａ（以後マウント部と呼ぶ）
と１、Ｃチップ電極（図示せず）から金又はアルミワイ
ヤー４ａで外部に取り出すための接合部５ａ（以後ボン
ディングパッド部と呼ぶ）とキャップシールするための
シールリング６ａの取付け部にタングステンメタライズ
を施し、焼成後Ｎｉメッキと施してシールリング６ａを
Ａｇ−ａ、ロウ付けする。次にＮｉメッキをして１．０
〜１．５μの厚さのＡｕメッキを行う。このパッケージ
はボンディングパッド部５ａのセラミックの積層部７ａ
を通つて内部壁から外壁に通じており、外部電極Ｂａが
パッケージの側面と底面に形成される。この構造のパッ
ケージにチップ２ａがマウント部３ａに接着されＡｌは
又はＡｕワイヤーによりチップ電極とボンディングパッ
ド部とが接続される。次にシールリング６ａにコバール
キヤツプ９ａがシームウエルド封止されて従来構造のチ
ップキャリヤー型半導体装置がつくられる。しかし、第
３図の如く回路基板に取り付ける作業において回路基板
のパターン接合部とパッケージの外部電極部の位置合せ
が難しいと共に接合後の検査力士にくく、接合強度が弱
いことが挙げられる。また、このパッケージに使用され
る回路基板はほとんどがアルミナセラミック基板でつく
られている。この理由は、熱膨脹差による接合部のはが
れとチップから発生する熱をより良く放散させるために
アルミナセラミック基板が使用されている。またセラミ
ック基板で製造される大きさは５ｃｍ□以上の大きさは
むずかしく、エポキシガラスやポリイミド樹脂によるプ
リント配線基板は５６×４０ｃＴｎのものまて作れるの
で実装密度が向上する。また、高集積度、高い消費電力
を要するチップには従来のパッケージでは熱抵抗的、接
合強度的に満足するパッケージと回路基板ではなかつた
。本発明は上記欠点を除去し、高信頼度、低価格のチッ
プキャリアー型半導体装置を提供するものである。However, there have been problems with the bonding method, bonding strength, heat dissipation, material of the circuit board, etc. in the method of bonding the package and the circuit board. These problems will be explained with reference to a perspective view of the conventional package structure in FIG. 1, a cross-sectional view in FIG. 2, and a cross-sectional view of the package bonded to a circuit board in FIG. 3. The package includes a semiconductor element 2a (hereinafter referred to as 1, C chip) on a ceramic substrate 1a.
Chip mounting part 3a (hereinafter referred to as the mount part) to which the chip mounting part 3a is attached
1. Tungsten metallization is applied to the bonding part 5a (hereinafter referred to as the bonding pad part) for taking out the C-chip electrode (not shown) to the outside using gold or aluminum wire 4a, and the attachment part of the seal ring 6a for cap-sealing. After firing, the seal ring 6a is plated with Ni and brazed with Ag-a. Next, Ni plating is applied to 1.0
Perform Au plating to a thickness of ~1.5μ. This package has a ceramic laminated portion 7a of a bonding pad portion 5a.
The inner wall communicates with the outer wall through the package, and external electrodes Ba are formed on the side and bottom surfaces of the package. In a package having this structure, a chip 2a is bonded to a mounting portion 3a, and the chip electrodes and bonding pad portions are connected by Al or Au wires. Next, the Kovar cap 9a is seam welded and sealed to the seal ring 6a to produce a chip carrier type semiconductor device having a conventional structure. However, as shown in FIG. 3, it is difficult to align the pattern bonding part of the circuit board and the external electrode part of the package during the work of attaching it to the circuit board, and it is also difficult for a sumo wrestler to inspect the package after bonding, and the bond strength is weak. Additionally, most of the circuit boards used in this package are made of alumina ceramic substrates. The reason for this is that an alumina ceramic substrate is used to better dissipate the heat generated from the chip and peeling of the joint due to differential thermal expansion. Furthermore, it is difficult to manufacture ceramic substrates with a size of 5 cm square or more, and printed wiring boards made of epoxy glass or polyimide resin can be made as large as 56 x 40 cTn, which improves the packaging density. Furthermore, for chips that require high integration and high power consumption, conventional packages and circuit boards have not been satisfactory in terms of thermal resistance and bonding strength. The present invention eliminates the above drawbacks and provides a highly reliable, low-cost chip carrier type semiconductor device.
本発明のパッケージは、熱放散、接合強度の向上、接合
を容易にする為に、又原価低減のためにアルミナ回路基
板からエポキシガラスやポリイミド樹脂によるプリント
配線基板に変更した場合でも接合のはがれがないように
例えば接合部形状を水平面の接合からつば部にある水平
面と壁にある垂直面の接合面を持つようなパッケージ構
造を有し、本パッケージに合う回路基板は、本パッケー
ジが接合する穴を有し、回路基板穴の周囲に配置せられ
た配線パターンとパッケージ壁部とつば部の接合部にお
いてＰｂ−Ｓｎ半田等において接合されたものである。
本発明を実施例により説明する。The package of the present invention is designed to improve heat dissipation, improve bonding strength, facilitate bonding, and prevent bonding from peeling even when changing from an alumina circuit board to a printed wiring board made of epoxy glass or polyimide resin in order to reduce costs. For example, a circuit board that fits this package has a package structure in which the joint shape has a horizontal surface joint to a horizontal surface on the collar and a vertical surface on the wall. The wiring pattern arranged around the circuit board hole is joined to the package wall and the flange using Pb-Sn solder or the like.
The present invention will be explained by examples.
第４図は本実施例の斜視図、第５図は断面図、第６図は
回路基板に実装した断面図を示す。セラミック基板１ｂ
にＩＣチップ２ｂを接着するマウント部３ｂを設ける為
に、該基板１ｂの経よりも若干小さい第１セラミック枠
１１ｂを積層し、次に第１セラミック枠１１ｂの経が同
じで内径が若干大きい第２セラミック枠１２ｂ１を第１
セラミック枠１１ｂの上に積層し、段部を形成しボンデ
ィングバッド部１５ｂとマウント部３ｂ１ボンデングバ
ッド部５ｂ１ボンディングバッド部５ｂからセラミック
の積層部７ｂを通つて外部電極８ｂまで、更にシルリン
グ６ｂの取付部などがタングステンメタライ．ズにより
印刷され高温て焼成、表面処理シールリングのロウ付な
どが行われてパッケージが完成する。更に必要があれば
パッケージ裏面に熱放散を向上する目的で銅などのヒー
トシンク１３ｂを取付けても良い。このようにして得ら
れたパツケー．ジに１Ｃチップ２ｂを固着した後にアル
ミ又は金ワイヤー４ｂよりチップ電極（図示せず）とボ
ンディングバッド部５ｂとを結線し、キャップ９ｂをシ
ームウエルド封止すると本実施例のチップキャリアー型
半導体装置が完成する。第６図は本半・導体装置を回路
基板１４ｂに接続した状態の断面図を示す。又、第７図
は本発明の第２の実施例の断面図を示す。回路基板１４
ｂは、従来のようにセラミック基板でなくエポキシガラ
スやポリイミド樹脂によるプリント配線基板の所定の位
置に本実施例の第１、第２セラミック枠１１ｂ，１２ｂ
が接合できる経の穴１５を設け、該穴１５の周辺に半導
体装置の外部電極８ｂに合致する配線パターン１６ｂが
設けられ、該外部電極８ｂと配線パターン１６ｂとをＰ
ｂ−Ｓ畔田付けにより段部の水平面と垂直面で接合され
るために接合強度が向上する。又、本発明の実施例の半
導体装置を説明する断面図第５図、第６図のパッケージ
の裏面にはヒートシンクが設けられているが、なくても
良い。又接合する穴とパッケージの外壁の相対寸法を０
．２Ｔｗｔ程にコントロールすることによつて接合部の
半田付の位置決めに簡単になる。更に本パッケージ構造
と接合構造にすることによつてパッケージにヒートング
を設けることが可能で、回路基板もセラミック基板から
エポキシガラス又はポリイミド樹脂に切え可能であるた
めに低熱抵抗化、高密度実装、高信頼性安価な回路基板
が使用できるチップキャリアー型半導体装置を提供する
ことが可能となつた。図面の簡単な説明第１図、第２図
、第３図は従来の半導体装置のそれぞれ斜視図、断面図
、回路基板に接合した状態の断面図であり、第４図、第
５図、第６図は本発明の実施例の半導体装置のそれぞれ
斜視図、断面図、回路基板に接合した状態の断面図を示
す。FIG. 4 is a perspective view of this embodiment, FIG. 5 is a sectional view, and FIG. 6 is a sectional view of the device mounted on a circuit board. Ceramic substrate 1b
In order to provide a mount part 3b to which the IC chip 2b is attached, a first ceramic frame 11b, which is slightly smaller in diameter than the substrate 1b, is laminated, and then a second ceramic frame 11b, which has the same diameter but a slightly larger inner diameter, is laminated. 2 ceramic frame 12b1 as the first
It is laminated on the ceramic frame 11b to form a step part, and from the bonding pad part 15b, the mounting part 3b1, the bonding pad part 5b1, the bonding pad part 5b passes through the ceramic laminated part 7b to the external electrode 8b, and then the sill ring 6b is attached. The parts are made of tungsten metal. The package is completed by printing, firing at high temperature, and soldering the surface treatment seal ring. Furthermore, if necessary, a heat sink 13b made of copper or the like may be attached to the back surface of the package for the purpose of improving heat dissipation. Packets obtained in this way. After fixing the 1C chip 2b to the chip, the chip electrode (not shown) and the bonding pad part 5b are connected using the aluminum or gold wire 4b, and the cap 9b is sealed by seam welding to form the chip carrier type semiconductor device of this embodiment. Complete. FIG. 6 shows a sectional view of the present semiconductor/conductor device connected to the circuit board 14b. Further, FIG. 7 shows a sectional view of a second embodiment of the present invention. Circuit board 14
b, the first and second ceramic frames 11b and 12b of this embodiment are placed at predetermined positions on a printed wiring board made of epoxy glass or polyimide resin instead of a ceramic board as in the conventional case.
A wiring pattern 16b that matches the external electrode 8b of the semiconductor device is provided around the hole 15, and the external electrode 8b and the wiring pattern 16b are connected to each other.
b-S ridge attachment improves the joint strength because the joints are made on the horizontal and vertical surfaces of the stepped portions. Further, although a heat sink is provided on the back surface of the package in FIGS. 5 and 6, which are cross-sectional views illustrating the semiconductor device according to the embodiment of the present invention, it is not necessary to provide a heat sink. Also, set the relative dimension of the hole to be joined and the outer wall of the package to 0.
．． By controlling the torque to about 2 Twt, it becomes easier to position the solder joints. Furthermore, by using this package structure and the bonding structure, it is possible to provide a heating element in the package, and the circuit board can also be changed from a ceramic board to an epoxy glass or polyimide resin, resulting in lower thermal resistance, higher density mounting, and It has now become possible to provide a chip carrier type semiconductor device in which a highly reliable and inexpensive circuit board can be used. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1, 2, and 3 are a perspective view, a cross-sectional view, and a cross-sectional view of a conventional semiconductor device bonded to a circuit board, respectively, and FIGS. FIG. 6 shows a perspective view, a cross-sectional view, and a cross-sectional view of a semiconductor device according to an embodiment of the present invention in a state where it is bonded to a circuit board.
第７図は本発明の他の実施例を示す断面図てある。尚、
図において、１ａ，１ｂ・・・・・・セラミック基板、
２ａ，２ｂ・・・・・ＩＣチップ、３ａ，３ｂ・・・マ
ウント部、４ａ，４ｂ・・・・・・金またはアルミワイ
ヤー、５ａ，５ｂ・・・・・・ボンディングバッド部、
６ａ，６ｂ・・・・・・シールリング、７ａ，７ｂ・・
・・・・積層部、８ａ，８ｂ・・・・外部電極、９ａ，
９ｂ・・・・・・コバールキヤツプ、１０ａ・・・・・
・セラミック回路基板、１１ｂ・・・・・・第１セラミ
ック枠、１２ｂ・・・・・・第２セラミック枠、１３ｂ
・・・・・・ヒー１・シング、１４ｂ・・・・・・エポ
キガラス又はポリイミド製プリント配線基板。FIG. 7 is a sectional view showing another embodiment of the present invention. still,
In the figure, 1a, 1b... Ceramic substrate,
2a, 2b...IC chip, 3a, 3b...Mount part, 4a, 4b...Gold or aluminum wire, 5a, 5b...Bonding pad part,
6a, 6b... Seal ring, 7a, 7b...
... Laminated portion, 8a, 8b... External electrode, 9a,
9b... Kovar Cap, 10a...
-Ceramic circuit board, 11b...first ceramic frame, 12b...second ceramic frame, 13b
・・・・・・Heat 1・Thing, 14b・・・Epoxy glass or polyimide printed wiring board.
Claims (1)
るチップキャリアー型半導体装置の周囲の側壁に段部を
設け、該段部に外部電極が設けられた事を特徴とする半
導体装置。 ２ セラミック基板にメタライズを施し積層して得られ
るチップキャリアー型半導体装置の周囲の側壁に段部を
設け、該段部に外部電極が設けられ、更に該基板にヒー
トシンクを取り付けたことを特徴とする半導体装置。[Claims] 1. A semiconductor device characterized in that a chip carrier type semiconductor device obtained by metallizing and laminating a ceramic substrate has a stepped portion on the peripheral side wall, and an external electrode is provided on the stepped portion. . 2. A chip carrier type semiconductor device obtained by metallizing and laminating a ceramic substrate is provided with a stepped portion on the peripheral side wall, an external electrode is provided on the stepped portion, and a heat sink is further attached to the substrate. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55008532A JPS6041858B2 (en) | 1980-01-28 | 1980-01-28 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55008532A JPS6041858B2 (en) | 1980-01-28 | 1980-01-28 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56105656A JPS56105656A (en) | 1981-08-22 |
| JPS6041858B2 true JPS6041858B2 (en) | 1985-09-19 |
Family
ID=11695751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55008532A Expired JPS6041858B2 (en) | 1980-01-28 | 1980-01-28 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041858B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5875859A (en) * | 1981-10-30 | 1983-05-07 | Fujitsu Ltd | Semiconductor device |
| JPS58149566U (en) * | 1982-03-31 | 1983-10-07 | 株式会社デンソー | distribution type fuel injection pump |
| JPS5967661A (en) * | 1982-10-12 | 1984-04-17 | Hitachi Ltd | Semiconductor device |
| US5455385A (en) * | 1993-06-28 | 1995-10-03 | Harris Corporation | Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses |
-
1980
- 1980-01-28 JP JP55008532A patent/JPS6041858B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56105656A (en) | 1981-08-22 |
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