JPS6042422B2 - Pulse cycle generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for generating a series of spaced, interconnected pulses.

Such pulse trains are particularly needed for testing storage products (storage with buffers).
Various pulses are used in testing storage products.

A pattern is applied to the storage (see Figures 4 and 5). The response of the storage product with respect to the pulse pattern is recorded and compared with the theoretical value to be achieved. A comparison of these two values determines whether the storage product performs as required, ie, whether there are any defects. Initially, the pulse train generated is theoretically given by the specifications of the storage product.

In order to generate these theoretical values, a pulse train must specifically be generated by a pulse pattern generator. To date, storage products are tested on hardware test equipment specifically designed for this particular product.

However, such hardware testing equipment has the disadvantage that it can only be used for certain specific storage products. Furthermore, the hardware testing device described above has the disadvantage of allowing what is called a hold time. During these time periods, the storage product being tested undergoes certain changes, such as capacitor discharge or charge shifting. An optimal test is that when an event related to a storage product occurs, one pulse train must be released by another pulse train, i.e. the original pulse train should be replaced by a new pulse train. must be taken into account. Conventional hardware test equipment requires a specific time interval to switch from one pulse train to another. Switching without gaps has not been possible for technical reasons, since switching is only carried out after the transient switching action has decayed. However, there is a drawback that during the holding period, new states may occur in the storage product being tested. In order to eliminate these drawbacks,
A method and apparatus have been devised for generating a series of spaced, interconnected pulses, which are described in detail below.

This was devised. However, the process and equipment devised to carry out the process are limited by the pulses that can be generated.
The disadvantage is that the time resolution of the cycle is 10 nanoseconds. That is, the devised process is approximately 10
For nanosecond rasters and above, pulse cycles are created only from 30 nanoseconds. Each pulse cycle begins with a short time interval cycle start pulse. From this cycle start pulse within a cycle, a pulse of a predetermined width and a predetermined spacing can be obtained as a cycle start. Even higher temporal resolution of the pulse cycle is not possible with the method originally devised and the equipment originally devised to carry out the method due to speed limitations of even the most advanced circuit technology. be.

That is, pulse cycles of, for example, 30, 40, 50, 60, 90 nanoseconds are possible;
Pulse cycles of 37, 43, 57 or 69 nanoseconds are not possible. However, for many applications especially high time resolution pulse cycles (e.g. 1 nanosecond)
is necessary, for example, to test high-speed storage products. Therefore, it is an object of the present invention to first consider, without including hitherto unknown high speed circuits
It is an object of the proposed method to provide a means of higher resolution in time of spaced and interconnected pulse cycles.

Firstly, the first devised method and apparatus for generating spaced, interconnected pulse cycles will be described.

FIG. 5 shows in very schematic form the pulse pattern applied to the storage product 21 for testing purposes, ie the pulse pattern generated by the programmable pulse pattern generator 20. There is.

A continuous pulse train is applied to the storage in one or more lines. Since the pulse pattern generator is programmable, it can be used universally for different storages. As referenced in detail below, the programming language used allows for the inclusion of time indicators in each instruction. The above times indicate the total time during which the above instructions (one product cycle) with possible branch operations are executed. In other words, the above time indicates the interval until the start of the next instruction. FIG. 6 schematically depicts pulses at different times to illustrate the generation of a series of spaced, interconnected pulses by the circuit of FIG.

Pulses 11 and 2 shown in FIG. 6 are applied to the storage product. The time Tv, referred to as the product cycle, consists, for example, of the time from the trailing edge of one pulse to the trailing edge of the next pulse. Let us assume that under certain conditions of the product cycle, the changeover from one pulse train to the next occurs without any intervals. However, such a condition already appears at time TcOn before the end of the product cycle. The above product cycle must be followed without any intervals by another product cycle. Therefore, the occurrence of the next cycle must already be ready at time TcOn. This is shown in more detail in the schematic diagram of FIG.

Let us assume that each cycle is generated by a specific program part, for example program parts Pl, P2, which are stored in different locations of the computer storage 1. If the generation of cycles is, for example, a cycle generated by program portion P1 directly followed by a next cycle generated by program portion P2, then the program must branch from program portion P1 to program portion P2. The branching described above is executed by what is called a branching operation. Hence,
Time T. )n, if there exists a condition that the next cycle has to be generated, for example, by program part P2, then the branch operation to program part P2 has already occurred at this time T. x. It is executed in n. Therefore, the following two operations are executed in parallel so as to move at time TcOn. (1) Further execution of pulse 12.

(2) Execution of a branch instruction to program portion P2.

After the end of pulse 12, as described in detail below,
Let us assume that the branch instruction has already been executed so that from time Te a new cycle generated by program portion P2 follows without any intervals.

In other words, while the branch operation is in progress, this old product cycle continues to run towards its end. 8th
As shown in the simplified diagram of the figure, oscillators 22 and 23 are used according to the prior art to generate two successive pulse trains.

Let us assume that both oscillators are selectively connected to the connected output line by switch 24. However, when cycles generated by oscillator 22 are switched to cycles generated by oscillator 23, a transient switching operation typically occurs. It is not possible to determine a specific exact time of the switching instant after the decay of the transient switching action that always occurs. The above disadvantages are not observed in the originally conceived system, which is shown in a highly simplified manner in FIG. FIG. 4 shows three consecutive pulse trains, namely pulse trains 1, 2 and 3.

Each program cycle of the pulse train is of the same length.

One program cycle extends along the downward direction from one mark to the next perfectly aligned mark on the time axis.

In FIG. 4, for example, program portion P1 (FIG. 7)
The pulse train 1 generated by P2 consists of a total of three 80 nanosecond program cycles, and the program portion P2
The pulse train 2 generated by (Fig. 7) is 17 in total.
Pulse train 3 consists of two program cycles of 0 nanoseconds and is generated by program portion P3 (FIG. 7).
consists of two program cycles of 50 nanoseconds each. A pulse occurs in each program cycle within the same pulse train. The start of the pulse can coincide with the start of the cycle, but depending on predetermined data, the start of the pulse can also occur only after a predetermined period of time after the start of the cycle. The length of the above pulse can be changed based on predetermined data, but
All pulses have the same relationship in a pulse train and in all program cycles of the same pulse train. For better understanding, while the respective circuits of FIGS. 2 and 9 are used to generate the start of a program cycle, the program cycle pulse may be generated by the conventional means referenced below. Let me explain what happens.

The first circuit devised (Fig. 9) mainly consisted of an oscillator 19,
Down ◆ Consists of counter 3 and storage 1.

With this connection, only one oscillator needs to be connected to the down counter 3. Down counter 3 starts running with a starting count read into this counter from the addressed location of storage 1. The start count corresponds to the respective time given to programmed instructions. Down counting is performed at a frequency of, for example, 100 megacycles/second. (For higher frequencies,
Even the most advanced available circuits are not used because speed limits exist. ) The count pulses are spaced 10 nanoseconds apart. During down counting,
Before reaching count zero, certain measures are taken. For example, 20 nanoseconds before the end of counting to count zero, preparations are made to load a new starting count into the down counter. If the old counting operation is continued, a new starting count is loaded into the down counter upon reaching count zero. Therefore, a new down count can be added without any waiting time to accept the new starting count.
It is guaranteed that the counting operation continues the old down counting operation without any interval. For example, when the old down counting operation is continued towards zero, and then if a new starting count is loaded into this counter following the old operation, then this There will be a period of time like this. Considering time-consuming branching operations, we need to, for example,
The test is performed nanoseconds in advance.

If there is a branch condition, this branch operation is already started at this time and gives a new starting count at a time before the old counting operation ends, and the new starting count is loaded into the counter at the last time of the old down count cycle. . Details of this circuit are shown in FIG. 2 and will be discussed in detail below. The pulse to start the cycle is provided by the down counter. For the moment, let us just point out that an abrupt cycle start pulse is generated on line 15 to fix the cycle start.

After the execution of one cycle, a new cycle start pulse is generated again and all the cycles follow each other without any interval.

Starting from the leading edge of the cycle start pulse, pulses with a predetermined time relationship are generated during a cycle by conventional means, as shown, for example, in FIG.

FIG. 2 schematically shows the circuitry for loading the starting count into the downcount 3 from the addressable storage 1 and the detection circuitry for determining the particular count. The detection circuit is also used to prepare the down counter 3 for loading a new starting count from the storage 1. This reloading is executed at the same time as the count reaches zero when counting down the counter 3. By means of clock line 9 and line 10, counter 3 receives pulses of, for example, 100 megacycles/second.

The counter can be configured, for example, as an 8-bit binary counter. The counter counts 1, 2, 3, 4, 5,
It has output lines 4 for 6, 7 and 8. count 2
All outputs of the counter 3 are connected to the AND gate 5 except for the output of the counter 3. Then there is the following correlation: binary 0 = negative input signal to the AND circuit; binary 1
= There is a positive input signal to the AND circuit. AND gate 5 is on when all signal input lines are negative;
It is also assumed that the counter 3 reaches a count of 2 during this operation.

At this count of 2, AND gate 5 provides an output signal. ``Because all input lines of the counter are negative and the output line of count 2 is not connected to the AND gate. Let us now assume that line 8 is also negative. At that time, the signal applied to the output line 6 of the AND gate prepares the flip-flop 7. Flip-flop 7 provides an output signal at output Q of line 8 when the positive leading edge of the next counting pulse is present on clock line 9, or an inverse of this output signal at output O of line 12. supply. Based on the signal on line 8, the AND gate 5 is rendered non-conductive, while the signal on line 12 causes a new starting count to be sent from storage 1 to the down counter at the next clock signal applied to lines 9 and 10. Let them receive it.

This load operation is performed by counter 3 by the current count pulse.
Executed at the same time as the old contents of are counted down to the value zero. After loading the new output value, a new down counting operation then begins again.

The signal on line 8 is held as long as there is an output signal on line 6. However, this condition is only satisfied for count 2. The actual time to start the pulse train is provided on line 12 from the O1 output of flip-flop 7.

A connecting line 13 is connected from line 12 to flip-flop 14 . When a signal is applied to line 13, the output of flip-flop 14 is activated (in voltage steps). This voltage step is applied to line 16 so that line 15 is again deactivated.
, delay device 17 and feedback via line 18. Thus, a short cycle start pulse generated by delay device 17 is used in line 15.

(See Figure 10 for the occurrence of pulses during one cycle.) After the end of one cycle, the occurrence of a new cycle start pulse follows without any interval.

The duration of the cycle is predetermined by a program instruction and is available in storage 1 as a starting count. These circuit operations ensure that the new starting count is loaded into counter 3 at the same time that the old contents of the counter reach the value zero.

In a specific embodiment of the pulse generator, for example, a 100 megacycle/second oscillator provides a respective pulse interval of 10 nanoseconds. Therefore, a check for count 2 means that this counter is checked 20 nanoseconds before performing a down counting operation in order for the counter to begin a new load operation.

Branch operation on storage 1 (program branch)
If there is, for example 2 to perform this branch operation
Consideration must be made that a period of 50 nanoseconds is required.

This means that it must be found out about 50 nanoseconds before the downcounting operation whether such a branch condition actually exists. If so, this branch operation must be started already at this time, so that the new starting count supplied to the counter as a result of the branch operation is available before the old down-counting operation is executed and then loaded into the counter. Must be. Therefore, a test has to be made at a preset time and various detector circuits (not shown) similar to the above detector circuits are used to find out whether the branch condition needs to be met or not. Accordingly, the test must be performed, for example, 50 nanoseconds before the down-counting is performed, which in this example corresponds to 5 counts.

This specific time is predetermined by the system hardware. This ensures that branch operations are performed during the remaining time until the end of the down counting operation. Let us assume that a device consisting of a storage with buffers arranged in series is to be tested.

The device (hereinafter referred to as the product) must be tested with each pulse train or pulses having different predetermined cycle times. The different pulse trains must follow each other without any interval. During the product test, the buffer is loaded successively with pulse trains that follow each other without any intervals.

The buffer information is then written in parallel to a predetermined specific address in storage. Subsequently, the buffer is loaded again and its contents are written to the storage address that has changed by that time. During these two operations, the contents of the buffer or storage are read to find out whether the product is operating correctly by comparing it to a minimum value. A program is used to generate a periodic train of different sequential pulse trains.

The programming languages most commonly used for this purpose consist of various statements. The program statement has the following general structure. 1...
・・Address■・・・・Operation code■・●●・Condition■・・・Cycle time■・・・Address correction■・・・Control bit■・・...Data ■ ...Timing address I: The above address is the program's brush.
It shows the

A part program that generates a specific pulse train is stored based on this address.
Ru. Address ■: The above operation code determines, among other things, whether the program is executed at the address that directly follows in storage, or whether a branch operation is performed.
It shows whether the Address ■: The above conditions are used when the operation code is executed, for example, when a specific storage address is reached, or when a specific error occurs.
Indicates if the storage being tested is contaminated. Address ■: The above cycle time is a pulse cycle.
Indicates the period of the file.

(These data are provided by the specific product.) Address ■: The above address modification provides data that increases the buffer address or storage address, for example, every cycle.

Address ■: The above control bits are
For example, it controls writing to and reading from buffers or storage, respectively.

Address ■: The above data is written during the cycle.
Hail data pattern information.

Address ■: The above ゜゜timing゛ is applied to the product.
Provides information on pulse length and pulse interval. The start pulse of line 15 starts a pulse pattern whose data is predetermined by the specific product and whose coarse pulses according to the pulse width and pulse interval are these during the cycle time. Generated according to data.

Further details are provided in connection with FIG. In other words, the cycle start pulse generated is applied to line 15 of flip-flop 14.

The cycle start pulse is generated by the circuit described in connection with FIG. 2 in accordance with programmed instructions. The coarseness of each pulse train is predetermined by the storage product being tested and must be taken into account in the respective program instructions. FIG. 3 schematically shows a number of count pulses. The numerical markings placed on the count pulses give the counts produced by each count pulse. Following the down count operation, the three pulses on the left result in a count of 3, 2, 1. The next pulse further to the right produces a count of zero. However, the second
The circuit shown is designed so that it does not actually reach zero count since the new starting count is already loaded into the down counter at that time. The abscissa representing the pulses in FIG. 3 indicates time. The times Tl, t2, t3, t4 and T5 given in this figure must be considered in connection with a concrete embodiment of the circuit according to FIG. Therefore, time t1 is when a counting pulse is applied to the down counter, resulting in a count of 2 from a count of 3. Due to the delay introduced by the counter itself, a count of 2 appears at the counter output at time T2.

At time T3, a signal appears at the output of AND gate 5 due to the AND gate's own delay, indicating that count 2 has been reached.

At time T4, both the count signal and the l output signal of AND gate 5 are present at flip-flop 7.

Therefore, the conditions for the flip-flop to provide a signal at the output are fulfilled. The output of the flip-flop 7 becomes valid at time T5.

The time error between T4 and T5 is due to the delay introduced by flip-flop 7 itself. The output signal of this flip-flop 7 is used to prepare the counter for reloading a new starting count.
FIG. 10 shows a circuit that generates a pulse after the cycle start pulse is generated.

The cycle start pulse generated at line 15 in FIG. 2 during the current cycle has a predetermined width in relation to its leading edge in time and a predetermined distance from the leading edge of the cycle start pulse. It is used to generate a pulse with . This work is not new and the means used to solve this problem are also conventional and therefore not an object of the present invention. However, for the sake of thorough understanding, the embodiment of FIG. 10 shows a method for generating one pulse within one program cycle. Let us assume that the leading edge of the cycle start pulse marks the start of the cycle. A cycle start pulse is applied to line 15 to delay device 25. The delay device has at its output a plurality of output lines 32a or 32n. Each of these output lines is associated with a specific delay time. A plurality of these output lines 32a to 32n are connected to a multiplexer circuit 27. The multiplexer circuit 27 receives on line 38 from the programmable storage 30 an instruction by which the output line of the delay device 25 is selected for a particular delay time. The selected delay time line is switched from the multiplexer circuit to its output 33 and is applied to the flip-flop 29. The appearance of the delayed leading edge of the cycle start pulse causes flip-flop 29 to switch to present a voltage step at its output 37. This voltage step is the starting point of the pulse in one cycle. The end of the pulse on line 37 is determined by the next operation. A line 34 from the output 33 of the multiplexer 27 is connected to a second delay device 26 .

The delay device 26 has a plurality of output lines 35a to 35n with different delay times. These lines are coupled to a second multiplexer circuit 28 which is interconnected to programmable storage 30 by lines 39. The appearance of the delayed leading edge of the cycle start pulse on line 33 causes this leading edge to pass through line 34, through delay device 26, and into programmable storage 30 of multiplexer circuit 28 by line 39. guided to a previously determined value. At the output of multiplexer circuit 28, the further delayed leading edge of the cycle start pulse is applied to line 36. This leading edge of the cycle start pulse then lines 3
At the output section of 7, the voltage step is set. is applied to line 36 of flip-flop 29 which erases and therefore terminates the generation of pulses during a certain cycle time. In short, the delay times of the delay devices 25 and 26 are programmed and selected by the storage 30. This produces a pulse of a predetermined width and a predetermined distance to the leading edge of the cycle start pulse.

Since the pulse generation in one cycle is always due to the cycle start pulse, the above programmable storage 3 is executed in parallel with the program in storage 1 (see Figure 2).
The presence of 0 is absolutely necessary as perfect time synchronization in the generation of the respective pulse trains.

The data in storage 1 determines the cycle start time, and the data in storage 30 determines the value of the pulses generated in each cycle. These values are changed in relation to the start of the cycle in terms of pulse width and pulse interval. The operations disclosed by the present invention for generating a series of spaced pulses with high time resolution and the apparatus for carrying out the above operations are described below with reference to the aforementioned operations as originally conceived. Ru. In the embodiment of the circuit in FIG. 2, a 100 megacycle/second crystal oscillator is used as clocking. Higher clock frequencies are currently not possible due to the speed of circuits used in modern technology. The shortest cycle duration achievable with a 100 megacycle/second oscillator according to the circuit disclosed in FIG. 2 is approximately 30 nanoseconds.

The leading edge of the pulse of each time line 15 initiates the cycle. If the cycle has a minimum length of 30 nanoseconds, there will be a 30 nanosecond interval between the leading edges of the pulses of line 15. The pulse generation for a given time resolution of the cycle is the first
0.

It is known from above that different cycle times can be programmed and generated to provide time values to the storage 1 (FIG. 2).

Due to the use of a 100 megacycle/second oscillator in the circuit of FIG. 2, only a 10 nanosecond raster cycle time can be initiated above 30 nanoseconds. This means that the successive cycle times differ by at least 10 nanoseconds if they are not the same. This is the reason for the disadvantage that cycle trains have a resolution of up to 10 nanoseconds, which is insufficient for many uses.

For example, testing of high speed storage products or testing of high speed logic circuits requires 1 nanosecond resolution.

A resolution of 1 nanosecond means that pulse cycles of, for example, 37 nanoseconds, 42 nanoseconds, or 83 nanoseconds can be generated.

Similarly, several cycles of e.g. 57 ns can be followed several times in succession, e.g. 1000 cycles of 57 ns, followed by a cycle of 32 ns, etc.
This could be followed by 500 cycles of 1000 nanoseconds, and so on. Consideration must be given to ensuring that all cycles are interconnected with no gaps between them, ie to avoid lag times caused by certain transient operations.

Circuits that can apply pulse cycles with 1 nanosecond resolution are known in the art.

For example, so-called VCO circuits (voltage-controlled oscillators) or fixed-setting oscillators addressed by multiplexer circuits. However, all these circuits present the disadvantage of being switched from one frequency to another.

That is, whenever the cycle time is changed, undesirable transient times appear. These prevent cycles from being interconnected at intervals, which is a disadvantageous effect for testing high speed storage products or high speed logic circuits, for example. In order to avoid these disadvantages, it is an object of the present invention to provide a method and apparatus for generating spaced and interconnected pulse cycles of even higher resolution.

In other words, it is possible to provide even smaller time rasters of pulse cycles (for example 1 nanosecond) without the need to use even higher speed, not yet known, circuits.

FIG. 1 shows a block diagram for generating spaced, interconnected pulse cycles with a time resolution of 1 nanosecond.

The parts of the circuit enclosed by dashed lines generally correspond to the circuit of FIG. 2, using the same reference numerals. In the present invention, the portions of the circuit indicated by thick lines have been improved. That is, flip-flop 700 (reference numeral 7 in FIG. 2) is shown as having an additional control line 70. The functions of the above control lines are controlled by the respective control pulses.
Delaying the switching of the flip-flop 7 by a specific predetermined value. It is. This type of flip-flop circuit is well known to those skilled in the art and will not be described here. Furthermore,
A connecting line 68 leads from line 8 to a new part of the circuit. In FIG. 2, line 15 is not connected to delay unit 25, whereas in FIG.
50-9, and a multiplexer circuit 51 is controlled and connected to switch one of these taps. As already pointed out, the 10th
The circuit shown in the figure is used to generate pulses with a predetermined time relationship within one cycle.

The function of the part of the circuit of FIG. 1 surrounded by the dashed line is that of the circuit of FIG. 2, which is known.

To this end, reference will also be made below to the effects of the parts of the circuit described above that have been improved according to the invention. To better understand the operation of the circuit of FIG. 1, reference is made to the pulse diagrams of FIGS. 13A and 13B.

FIG. 13A shows the cycle train Cl generated in the circuit of FIG.
An example of O-C2O-C3O is shown. Each cycle start pulse IClO, IC2O, IC3O is approximately 30 nanoseconds apart. That is, each cycle is determined by their leading edge. FIG. 13B shows the cycle sequence Cln-C2n- generated on line 57 by the circuit of FIG.
Indicates C3n. The pulses ICln, IC2n and IC3n of line 57 may have a spacing B of 37 nanoseconds from each other, for example, which determines the recycle time. Second
To better understand the circuit of FIG. 1 compared to the circuit shown, the two pulse trains of FIGS. 13A and 13B are shown aligned one above the other on the same time scale.

Pulses IClO, IC2O, IC3O (leading edge) are at time t
-10, t-20 and t-30, pulsed ICl
n, IC2n, IC3n (leading edge) at time t-1n, t-
2n, appears at t-3n. If this were to occur in the circuit of FIG. 2, the circuit would have different taps for the time delay such that the pulse train of FIG. 13A and the pulse train of FIG. 13B are 1 nanosecond apart. However, in this case the difficulties encountered are insurmountable. These difficulties are particularly apparent when attempting to generate several consecutive cycles of, for example, 37 nanoseconds.
This is because the pulses IClO, IClO, which then appear on line 15 (FIG. 2) at times t-10, t-20, t-30,
, IC3O must be gradually delayed.
In other words, pulse IC2O must be delayed by 7 nanoseconds to produce pulse IC2n, and pulse IC2O must be delayed by 7 nanoseconds to produce pulse IC2n.
3O must be delayed by 14 nanoseconds to produce pulse IC3n. Figure 13B shows the delay value (7 in the above example).
, 14 nanoseconds, etc.), indicating that this requires a complex delay line with many taps and response control of the taps. This impractical solution is avoided in the circuit of FIG. The circuit of FIG. 1 is provided with two registers 54 and 55 whose contents are applied to the adder circuit 53, in particular through lines 61 and 62. Like the carry line 64, the adder circuit has an output of a w-adic one-digit sum. Line 59 connects multiplexer control circuit 5 to activate the taps of delay line 50.
1 through line 58. Additionally, line 59 is returned to the input of register 55 through line 60. Register 54 receives its contents from programmable storage 56 over line 63. This storage 56 contains given values for a resolution of 1 nanosecond. In other words, if a cycle time of 37 nanoseconds is reached, storage 1 contains data for a cycle time of 30 nanoseconds and storage 56 contains an additional 7 nanoseconds of data. It is quite clear that the values in storage 56 range from 0 to 9. For the above example of a cycle time of 37 nanoseconds, the value 7 is applied to register 54 from storage 56 through line 63.

For the start of the cycle given by pulse ICln of FIG. 13B, register 54 contains a content of 7 and register 55 shows an initial content value of 0. During the cycle execution,
The contents of registers 54 and 55 are added by adder circuit 53 to yield a value of 7. This value of 7 is applied to register 52 through adder 1-digit sum output 59 and is applied to register 52 on line 60.
(used during the next cycle). The multiplexer control circuit 51 operates through the line 58 of the value 7 of the register 52 to switch the tap 50-7 to the output line 57. Therefore line 1
The pulse appearing at time t-20 in line 57 is pulse I on line 57.
It appears 7 nanoseconds later than C2n. Time t-2nI:
．． The next cycle C2n (FIG. 13B) during t-3n is generated as follows.

Since the cycle C2n again represents a cycle time of, for example, 37 nanoseconds, the value 7 is again read from storage 56 into register 54 through line 63. At this time, register 55 still contains the value 7 from the previous cycle Cln. The values of both registers 54 and 55 are added by adder 53 to yield the value 14. Since the one-digit sum output 59 of adder 53 passes only the last digit of the sum, ie, 4, register 52 also receives the value 4 for the switch of tap 50-4 of delay line 50 to output line 57. Addition of both values from registers 54 and 55 also results in the value in position 10 (i.e. 1 out of 14), so the carry line 64 of adder 53
is started. The carry line 64 is connected to a timing circuit 65.

The function of the timing circuit 65 is to generate a predetermined control pulse that is applied to the flip-flop 700 upon activation through the carry line 64. The purpose of the above control pulse is to delay the switching of flip-flop 700 by a predetermined amount, and thus one count after the down counter is loaded with the new output value.
This is to delay the down-counting operation by a clock. The implementation of delay switching by means of control pulses of such flip-flops is generally known, as indicated above, and therefore will not be described in detail.

The circuit in the portion of FIG. 1 enclosed by the dashed line has been optimized to provide 10 nanosecond resolution. For a better understanding of the circuit operation of FIG. 1 with respect to the above-described delayed down counting operation of counter 3 when there is a carry on carry line 64 of adder 53, reference is made to FIG. In the above figure, a series of count clocks is shown on line 9 from a particular time t1 to Tl2. These times are necessary to understand the operation of the circuit of FIG.
Time t1 to T5 is the third period associated with the circuit operation of FIG.
Corresponds to the times shown in the figure. For further understanding, the importance of the times t1 to T5 (FIG. 12) is once again pointed out (this time with reference to the circuit of FIG. 1). Time t1 is the time when a counting pulse (clock pulse) to increase the count from 3 to 2 is applied to the down counter.

Due to the delay introduced by the counter, a count of 2 occurs at the output of the counter at time T2. Starting from time T3, due to the delay of the AND gate, a signal appears at the output of AND gate 5, which signal indicates that count 2 has arrived.

At time T4, both the count signal and the output signal of AND gate 5 are present at flip-flop 700. Therefore, the conditions are met for flip-flop 700 to apply a signal to its output. The output of the flip-flop 700 is used starting from time T5.

The time difference between T4 and T5 is due to the delay caused by flip-flop 700. Flip-flop 7 above
The 00 output signal is used to prepare the counter for reloading with a new starting count. Regarding the time T6 to Tl2, it will be pointed out below.

Output line 1 of flip-flop 700 to counter 3
When the O signal is present on line 2 and the leading edge of the next counting pulse is present on line 9, the counter 3 registers at time T.
It will be loaded again at 7. From time T9 onward, counter 3
The value loaded into occurs at the output of the counter.

From time T5 onwards, the signal at the Q output of flip-flop 700 passes through line 8 to cause AND gate 5 to become non-conducting.

Therefore, the output value of counter 3 disappears and at time T8
Then, the flip-flop 700 flips ◆back. As a result, down counter 3 becomes flip-flop 700.
is returned to the down-counting state through line 12 of its O output. However, if there is a leading edge of a new counting pulse, counter 3 will change the time TlO
The above can be prevented because down counting can be started only at time Tl2 instead.
For this purpose, it is checked at time T5 whether a signal is present on carry line 64.

If the signal is present, after being delayed by flip-flop 66, the signal is produced at the output of flip-flop 66 at time T6. This signal occurs for a period exceeding time T7 (up to a maximum time T9). Moreover, in parallel, down counter 3 is loaded with the new output value from storage 1 at time T7 and flip-flop 700 is reset.

The signal on line 70 has priority over the signal clock on line 9. That is, the clock signal on line 9 cannot overcome the signal on line 70 at time T7. From time T9 onwards, the signal on line 70 can no longer be used, so the same starting count from storage 1 is loaded once again into down counter 3 at time TlO as in the loading clock described above.

Flip-flop 700 is reset at time Tll;
And this will already cause counter 3 to start. Down counting begins at the leading edge of the following count clock of line 9 at time Tl2.

These circuit steps confirm that the down-counting operation does not occur at time TlO, but only at time Tl2, delayed by 10 nanoseconds.
Under conditions where a 0 megacycle/second oscillator is used, the interval between count pulses of line 9 is 10 nanoseconds. ) down-counting ● This delay in the process causes the pulse IC3n to fall at time T3O (Figure 13A).
(Figure 13B) has been observed to appear after a total delay of 14 nanoseconds. That is, the total delay of 14 ns is the 10 ns delay caused by the delayed down counting of counter 3 plus the tap 50 of delay unit 50.
-4 with another 4 nanosecond delay with a corresponding control. It is important to note that the delay of the up and down counting operations of the present invention is accurate when applied to the time requirements of the count clock, ie, to a 10 nanosecond raster.

This application is achieved by the respective time relationships of the pulses occurring on line 70 in conjunction with adder 53. Each operation for a carry of the adder 53 is performed as follows. As soon as a carry pulse appears on line 64, flip-flop 66 is switched if there is a leading edge of the pulse on line 8.

After the delay of flip-flop 66, this condition also appears on line 70 at time T6. This condition holds until ending at delay unit 67 after a corresponding delay on line 69 entering the input of flip-flop 66 at time T9. The interval between times T6 and T9 is important for the respective synchronization delay of the down counter 3. flip flop 70
This interval must not be long so that 0 returns to the off condition at a time Tll after clock 10. In this way, pulse I of 37 nanoseconds after said pulse IC2n
C3n occurs on line 37.

Total delay of 14 ns between times T3O and T3l (13th
B) is thus divided into the corresponding taps of delay unit 50 and the delay time due to the down-counting process of counter 3, which delays by 10 nanoseconds (in this example). Due to the delay of the counter 3, it is possible to operate with a delay unit 50 having up to 1 tap, where the time delay can be flexible up to 1 nanosecond each. FIG. 11 shows a detailed diagram of the timing circuit 65.
Indicates grams. The timing circuit is a flip-flop 66.
and a delay unit 67.

The flip-flop 66 is connected to a clock line 68 (front-line triggering) and a data line 64 which is the carry line of the adder 53.
and a line 69 for resetting the flip-flop. The output of flip-flop 66 is connected through line 70 to flip-flop 700. The pulses on the output line 70 prevent the switching of the flip-flop 7 during the pulses. Furthermore, the output line 70 of the flip-flop 66
is connected through a delay unit 67 to reset input 69 of flip-flop 66. Flip-flop 66 also shows a control line 71 for activating the entire circuit. That is, when an activation pulse appears on line 71, flip-flop 66 produces a pulse on line 70 that switches the circuitry within the solid line area into a loaded state. It has been determined that even for the slowest addition operations, the carry occurs before the leading edge of the switch-off signal appears on line 8.

(Depending on the size of the number being added, different addition times appear in the addition circuit 53 defined as a binary adder.)
For example, the addition times for the sums 8+2=10 or 7+7=14 are different. This also shows that the carries occur at different times. The purpose of timing circuit 65 is to synchronize the carry with the load operation of counter 3. This is done in the specific manner described above. For further understanding, storage 1 and storage 56 have been separated in FIG.

(Storage 1 was used to store cycle time values with a time resolution within 10 nanoseconds, and storage 56 was used to store time values with a time resolution of 1 nanosecond.) These stores are combined into one storage. It is quite obvious that they can be combined. Therefore, the value of the cycle time as well as the 10 ns and 1 ns rasters is simply counter 3.
This merely allows the registers 54 and 54 to be used in parallel and synchronously. Registers 54, 55 and 5
2 is not an essential feature of the present invention, so their relationship is not shown.

Similarly, the clock line of register 52 extending from line 15 and registers 54 and 55 extending from line 8 are also not shown. Having previously described how the cycle time, which has a flexibility of 1 nanosecond, is determined by the leading edge of the cycle start pulse occurring corresponding to line 15, for the above given operation of the circuit of FIG. As can be seen, by applying these cycle start pulses to the above circuit of FIG.
It is possible to generate corresponding time-related pulses within a given cycle. The use of a circuit as disclosed in the present invention is not limited to being used to test high speed storage products or high speed logic circuits, but rather to switch frequencies at intervals (e.g. It is also applicable to switching transmission frequencies) or circuit-controlled generation of frequencies.

FIG. 14A shows the programmable pulse cycle Cl
, C2, C3, the pulse 11 generated according to the invention
, 12 and 13 are given. Details of the occurrence of these nopulses within each pulse cycle are given in FIG. As shown in FIG. 14B, pulses 11, 12 and 3 are used to key the same or different transmission frequencies Fl, f2, f3.

If pulses 1, 12 and 13 actually have a duration corresponding to the duration of pulse cycles Cl, C2 and C3, it is possible to switch between the same or different transmission frequencies at intervals without transient operation. It is possible. Keying of the transmission frequency by means of corresponding pulses is prior art and known to those skilled in the art and will not be described here.

The invention can also be used to generate predetermined frequencies.

FIG. 15 shows that, for example, in the modulation of the transmission frequency, a full frequency spectrum appears. Frequencies in the above spectrum ranging from f' to f1, ie frequencies respectively modulated around the actual transmission frequency FO, are grouped. If within the spectrum of said frequencies, each discontinuous frequency, e.g. F2'' or F3 This is likewise possible with the circuit described according to the invention.

By providing corresponding time values in storage 1 or storages 1 and 56, respectively, the individual cycle times are programmable, i.e. after a predetermined period in which a cycle start pulse appears, another cycle start pulse appears next. It has already been pointed out that this occurs due to the pulse ● cycle. The shortest cycle times achievable with today's circuit technology are on the order of 30 nanoseconds. The generation of several successive short cycle start pulses corresponds to providing a frequency corresponding to the cycle time. The programmability of the cycle duration allows different frequencies to be generated. Due to the 1 nanosecond resolution of the circuit disclosed by the present invention, approximately 2.3 megacycles/second (maximum estimated cycle time of approximately 655 microseconds)
Or frequency intervals of 1 megacycle/second (minimum estimated cycle time of about 30 nanoseconds) can be generated. Programmed switching of transmission frequencies can make data transmission secret if the programmed switching from one transmission frequency to another is known only to the sending and receiving sides.

Frequency is also the lower frequency range (the range of sound that can be heard by the ear)
But it can occur.

Is the principle of sound frequency generation based on high frequencies in the megacycle/second range? Same as life. This way you can generate sound frequencies and switch between them at intervals without any transients! It is possible to Although the human ear is generally not bothered by transients due to the ear's looseness, generating and switching sound frequencies without transients is of interest as a measurement technique. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a circuit for generating spaced interconnected pulse cycles with high time resolution.

FIG. 2 is a schematic diagram of a circuit for generating spaced, interconnected pulse cycles with low time resolution. FIG. 3 is a schematic diagram of count pulses at specific times associated with the circuit operation of FIG. 2; FIG. 4 is a schematic diagram of a continuous pulse train. FIG. 5 is a schematic diagram of a pulse pattern generator and storage product. FIG. 6 shows a schematic diagram of the coarse pulses at each time in order to understand the occurrence of spaced, interconnected pulse cycles in the circuit of FIG. Figure 7 shows a different example. 1 is a schematic diagram of a storage with a program portion for generating a pulse train; FIG. 8th
The figure is a schematic diagram of a circuit that generates a pulse train using two oscillators. FIG. 9 is a highly simplified circuit diagram illustrating the principle of generating a series of pulses connected to each other without any intervals by means of a down counter. FIG. 10 is a schematic diagram of a circuit that generates a pulse after the appearance of a cycle start pulse. FIG. 11 is a diagram showing the timing circuit of FIG. 1 in detail. FIG. 12 shows a schematic diagram of the coarse count clock at each time to understand the generation of spaced, interconnected pulse cycles of the circuit of FIG.
Figures 13A and 13B are schematic illustrations of pulse diagrams with 10 nanosecond and 1 nanosecond resolution. 1st
4A and 14B are schematic diagrams of the modulated transmission frequency of the pulse train generated by the circuit of FIG. 1st
FIG. 5 is a schematic diagram of discrete modulation frequencies arranged around a transmission frequency. 3...down counter, 1...storage means, 5,700...
・Trigger means, (AND gate and flip-flop), 14, 17...Output means, 50...
・Delay means (delay line), 51...Multiplexer, 53...Addition means, 55...Luster means, 56...Second storage means, 65
...Delay control means (timing circuit).

Claims (1)

[Claims] 1. A down counter that counts down by being driven by the input of a count clock; a storage means that stores a count value to be loaded into the down counter; trigger means for loading the pulse value stored in the storage means into the down counter in response to the down counter; and output means for outputting a pulse signal in response to the loading operation of the trigger means. In the pulse cycle generator, the trigger means can control the timing of the load by a specific first time using an external signal, inputs the output of the output means, and inputs the output of the output means to delay the load timing by a specific first time. A delay means having a plurality of taps for sequentially delaying and outputting signals by shorter time intervals, inputting the outputs from the plurality of taps, and controlling one output from the plurality of taps by controlling an external digital signal.
a multiplexer for selecting and outputting one value; and a multiplexer for adding at least two given values in response to the loading operation of the trigger means, and transmitting the value up to a predetermined digit of the added value to the multiplexer. an addition means for outputting a carry signal in response to a carry of the addition value from the predetermined digit; and an addition means for temporarily holding the addition value of the addition means and using it as a first value. register means for giving a second value to the addition means; second storage means for storing a numerical value to be given as a second value to the addition means; and delay control means for delay-controlling the trigger means in response to the carry signal. A pulse cycle generator characterized by having: