JPS6042497B2 - Shifter parity prediction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shifter parity reduction system.

Generally, input data with a parity of Pa is transferred to n by a shifter.
In the case of bit shifting, if the exclusive OR of n bits shifted in is PSI) and the exclusive OR of n bits shifted out is Ps°, then the parity PB of the output data obtained as a result of shifting is PB =PA(1)Ps
It is well known that it can be expressed as 11Ps0...(1).

By the way, the exclusive OR P of the data to be shifted in,
0 is the same as the exclusive OR of the data shifted out from the byte next to the input data of interest. Therefore, to predict the parity of output data, it is not necessary to calculate both the data to be shifted in and the data to be shifted out for each byte; for example, it is only necessary to calculate the exclusive OR of the data to be shifted out. become. Predicting parity using this method simplifies the hardware, but when performing a 7-bit shift, for example, the 7-bit data to be shifted out must be exclusively You have to find the logical sum,
In the end, it was necessary to prepare a logic circuit for performing an exclusive OR operation of up to 7 bits. An object of the present invention is to provide a shifter parity prediction method that can realize a circuit that can predict the parity of shifted data with a smaller number of gates.
The present invention deals with the parity Ps of shift-out data when 8-bit input data A0 to A is shifted leftward by n bits.

Then, the parity P of the shift-out data when shifted by (8-n) bits to the right. P＾=Ps0 and 1PSOR゜゜゜(2
), and its feature is that when calculating the exclusive OR of data to be shifted out, if the number of bits n to be shifted out is 4 bits or more, then (8- After calculating the exclusive OR for n) bits shifted in the other direction, the result is converted using the above equation (2).

Hereinafter, the system of the present invention will be explained in detail with reference to the illustrated embodiments.

FIG. 1 shows multiple bytes of data.

Each data D. ．． ．． Dl, D2, . . . consist of 8 bits and are now data D. A case will be described in which, when these data are shifted, the parity of the data resulting from the shift is predicted by the method of the present invention. When performing a shift of 3 bits or less in the right or left direction, calculate the exclusive OR of the data to be shifted out in each data, calculate these exclusive ORs, and perform the calculation based on method (1). Predict the parity of the shifted data. For example, when shifting 3 bits to the left, data D. The shift out bit of is A. , A1, and A2, first find the exclusive OR PsO of these bits. Data D. The shift-in bit when focusing on data D2
Since it is the data of the left 3 bits of , the exclusive OR of these bits PS! Find L. Equation (1) can then be applied to obtain the required result. Next, the case where the shift amount is 4 bits or more will be described.

To predict burrs when shifting 8-bit data in one direction by n (7≧n≧4) bits, calculate the exclusive OR Px of the shift-out bits when shifting (8-n) bits in the other direction. , and then use equation (2) to calculate n in one direction.
In the case of a bit shift, the exclusive OR of the shift-out bits is calculated and parity prediction is performed based on this.

For example, to explain parity prediction when shifting 6 bits to the left, the bits to be shifted out when shifting (8-6) bits to the right ~, the exclusive OR of A7 PX! Find the exclusive OR of the bits shifted out when 6 bits are shifted to the left using equation (2).
, is required. In the same way, the exclusive OR of shift-out bits in other data is calculated, so the (1st
) can obtain the desired prediction result. As mentioned above, in this method, even if the shift amount is 4 bits or more, the exclusive OR operation of shift-out bits can be performed using 4 bits or less, so in the end, the exclusive OR operation of up to 4 bits is required. All you need to do is have a circuit that performs calculations,
The hardware can be simplified to a much higher level.

Further, Table 1 shows whether or not the output contains an error when there is an error in the input data when predicting the parity of the shift output using this method.

As you can see from this table, both right shift and left shift are 4
If it is more than a bit, the error will appear in the adjacent byte. Having errors affect neighboring bytes in this way can be very useful for error tracking. Second
The figure shows an embodiment of a parity reduction circuit to which the present method is applied. The parity prediction circuit 10 includes a decoder 11 for decoding a shift amount given in binary numbers, an AND gate 12, NAND gates 13-26, inverters 27-29, and Kx OR gates 30-39. The truth table of the decoder 11 is as shown in Table 2, and when the shift amount n is 4 bits or more, a shift amount of (8-n) bits is given. To specify the shift amount, use terminal B4, ■,
This is done by applying binary data corresponding to the shift amount to b1, and input data shifted by a shift register (not shown) is applied to terminal ~A7.

Terminal P is an input terminal for parity data of this input data,
Terminal D is a terminal for inputting shift direction information, and RlJ is applied in the case of a right shift, and ROJ is applied in the case of a left shift. The data applied to terminal ~A7 is also sent to decoder 1.
NAND gate 13 that is selectively opened and closed according to the output of
.about.20, only the data of the bits that are shifted out is retrieved.

Then, the Ex-OR gates 30 to 35 calculate the exclusive OR of the shift-out bits. As already explained, in the case of a shift of 1 to 3 bits, the conventional calculation is performed, but in the case of a shift of 4 bits to 7 bits, the shift for a shift of 4 bits to 1 bit in the opposite direction is performed. The exclusive OR of the out bits needs to be computed. Therefore, the data in the shift direction and the terminal B4
The data from the Ex-OR gate 36 is input to the Ex-OR gate 36, and the output from the Ex-OR gate 36 is applied directly to one input of the NAND gate 22, and is also applied to one input of the NAND gate 21 via the inverter 28. . Therefore, when the shift direction is rightward and the shift amount is 3 bits or less, the gate 22 is opened, and when the shift amount is 4 bits or more, the gate 21 is opened. On the other hand, if the shift direction is leftward and the shift amount is 3 bits or less, the gate 21
is opened, and when the shift amount becomes 4 bits or more, the gate 22 is opened. The exclusive OR of the bits to be shifted out thus obtained is taken out from the NAND gate 23 and exclusive ORed with the output of the AND gate 12 at the Ex-OR gate 37. The output of this AND gate 12 is ROJ when the shift amount is 3 bits or less, and becomes parity inverted data when the shift amount is 4 bits or more. The output of this Ex-OR gate 37 becomes the exclusive OR of the shift-out bits. nand gate 2
5 is applied with the result S1 of the exclusive OR of the bits shifted in from the adjacent byte on the left, while the NAND gate 24 is applied with the result S2 of the exclusive OR of the bits shifted in from the adjacent byte on the right. is applied, and in the case of a right shift command, the NAND gate 24 is opened, and the Ex-OR gates 38 and 39 perform the exclusive OR of the shift-out bits of the currently focused byte, the result S2, and the parity data. The three are further exclusive-ORed, and the operation shown in equation (1) is performed to obtain the parity prediction result 0UT of the data shifted from the Ex-OR gate 39.

In the case of a left shift command, the result S1 is output from the NAND gate 26. In this way, the exclusive OR operation of shift-out bits can be performed up to 4 times, regardless of the amount of shift.
Since only bit operations are required, the number of gate circuits used can be greatly reduced. According to the method of the present invention, as described above,
Even if the shift amount is 4 bits or more, the exclusive OR operation of the shift-out bits requires less than 4 bits, so it is necessary to have a circuit that can perform an exclusive OR operation of up to 4 bits. This makes it possible to significantly simplify the hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the arrangement of shifted data for detailed explanation of the present invention, and FIG. 2 is a circuit diagram of a parity reduction circuit for a shifter to which the method of the present invention is applied.

Claims (1)

[Claims] 1 In the shifter parity prediction method that predicts the parity of the data after shifting by calculating the exclusive OR of the data to be shifted out, the number n of bits of the data to be shifted out and all bits of the data to be shifted If there is a relationship between n<N/2 with the number N, the exclusive OR of the shifted data is determined by the exclusive OR of the data to be shifted out, and there is a relationship of n≧N/2. In this case, the shifter parity reduction method is characterized in that the exclusive OR of the shifted data is determined by the exclusive OR of (N-n) bits of data.