JPS6042551B2 - semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit, and mainly relates to a memory cell drive circuit using bipolar transistors.

2. Description of the Related Art In a semiconductor memory circuit configured with bipolar transistors, a memory cell is known in which a diode with a resistor connected in parallel is used as a load of the transistor. This diode is turned off when the memory cell is performing a holding operation, and turned on depending on the information when writing or reading information. The diode can prevent the transistor of the memory cell from operating in saturation. The above-mentioned resistors have relatively large resistance values, so that the memory cell circuit operates with low holding power. FIG. 1 shows such a memory cell circuit 1, a driver circuit 2, and a write circuit 3.

Memory cell 1 is a current switching type and has a data line D.
, D, read transistors Q9, Q, O whose emitters are connected to information holding transistors Q, , Q, and load resistors Rc, , Rc. , a constant current source circuit I that flows an information holding current. c and the load resistances Rc, , Rc. Schottky barrier diodes D5 and D6 connected in parallel with
Consists of. Note that the transistors Q7 and Qlo or α and QlO, each having a common base and collector, are configured as so-called multi-emitter transistors in which two emitters are formed in one base region. Data line D
. , Dl is a constant current source circuit 1 for generating the current necessary for checking the contents of the memory cell in the read cycle and the write cycle. R0 and I0R1 are connected, and a drive transistor Ql is connected to the word line X1.
l is connected. The driver circuit 2 for reading and writing includes a transistor Ql for electrically isolating the memory cell from memory cells arranged in other columns. , Ql
3, transistors 9 and Q6 for level matching with the driver transistor Qll of the word line X1, and constant current source circuits 10.1 and I0D2.

The write circuit 3 includes emitter-coupled transistors Q1~
Q3, collector resistors R6, Rl, R2, and constant current source circuit 1. Consists of W. In this semiconductor memory circuit, memory cells (not shown) are actually formed in a matrix, and corresponding data lines and digit lines are provided, but for convenience of explanation, one memory cell and its surroundings are shown as above. The connection relationship with the circuit is shown. In the above circuit, the word line
1 is kept at a relatively low potential during the information retention period,
A high potential is set during information reading and writing periods.

The write circuit 3 receives write signals (2) and (V3) complementary to each other and a control signal (V1).

An example of a time chart of the signals V1 and V2 is shown in FIG. During the information holding and reading period, the control voltage V1 is at a high level, the transistor Q1 is on, and Q2 and Q3 are off. Output voltage at this time ■01,
(2) 02 is a value determined by RO-10w and is not related to input signals V2 and V3. When the signal V1 becomes low level during the write period, the transistor Q1 turns off.
Current 1. w flows into transistor Q2 or Q3. At this time, the output voltages ``01'' and ``02'' have values determined by the voltage drop across the resistors RO to R2. During the information retention period, the transistor Q of memory cell 1 changes depending on the stored information.
Either 7 or q is in the on state.

However, since the base potential is lowered due to the relatively low potential of word line X1, transistors Q9,
QlO is turned off. During this period, the resistance R
cl, R. The voltage developed across 2 is small and the voltage across diode D5,
D6 is in the off state.

During the information read period, the word line
The potential of 1 is raised.

The write circuit 3 is connected to the write circuit 3 via transistors Q5 and Q6.
The base potentials WO and VWl of the transistors Ql2 and Ql3 that receive output signals from the node Vc of the memory cell 1 are
The potential is set in advance between the potential of O and the potential of C1. If transistor Q7 is on and Q8 is off due to the level shown by the solid line in FIG.
The potential VcO of the node ■CO of the memory cell 1, that is, the base potential of the transistor QlO, is lower than the base potential ■WO of the drive transistor Ql2, which is the potential of the word line X1 minus the forward voltage of the diode D5; 1, that is, the base potential of the transistor 9 is approximately equal to the potential of the word line X1, and this potential is higher than the base potential ■W1 of the drive transistor Ql3.

- As a result, transistor q and drive transistor Ql2 are turned on, and transistor QlO and drive transistors Q and 3 are turned off. Due to the on-state of the drive transistor Ql2 and the off-state of the drive transistor Ql3, a sense output is generated at the terminals R2 and VRl. During the information writing period, for example, if the input signals V2 and V3 turn on the transistor O of the write circuit and turn off the transistor Q2, the drive transistor Q is turned on as shown in FIG.
The base potential of l3 ■''W1 is the node VCO of memory cell 1
, VOl, while the base potential VvvO of the drive transistor Ql2 is at the node (2).

0, ■.

1.

As a result, the base potential of the transistor QlO of the memory cell, that is, the base potential of the transistor Q5 becomes lower than the base potential of the transistors Q7 and Q9, and the node ① occurs. 1
The potential at the word line X1 becomes equal to the potential at the node V
The potential of cO is changed from the potential of word line X1 to diode D.
The forward voltage is lowered by 5.

However, as described above, during the information read period and write period, the drive transistor Ql2 or Ql3
The reference voltage applied to the base of

, VWl is the intermediate potential between the potential of the node ■CO and the node ■C1, that is, the potential of the word line X1 minus half the forward voltage of the diode D5 or D6. However, in the circuit shown in FIG. 1, the potential VW is
O, VWl are not appropriate values. As a result, the worst yang joint malfunction occurs. Transistor Ql when the characteristics change according to the broken line and the dashed-dotted line in FIG. Or, an example of the level of the base potential ■7 of Ql5 and the potential ■CO'9■X5 of the node VOO9■C1 is shown. Also, in FIG. 4, the broken line V. ．． . ″，
VWl'' and the dashed-dotted line V.'', ■o'', even when writing information, due to changes in the characteristics of the circuit elements, the base potential of the transistor Ql29Ql3 ■WO9V
Wl) The mutual potentials of the nodes ■CO9 and C1 no longer have an appropriate relationship. In order to create a high-speed operation circuit, the diodes D5 and D6 of the memory cell are constructed with Schottky diodes, but the forward voltage of these diodes is relatively small and the metal-semiconductor barrier causes a relatively large characteristic. Therefore, variations in the operating point of the circuit described above become a particularly important problem. The above-mentioned problem of malfunction also occurs in the case of fluctuations in operating voltage due to manufacturing variations. Erroneous write operations can be prevented by making the resistance value of resistor R2 in Figure 1 relatively large, but in this case, the signal amplitude becomes large, making it difficult to operate the circuit at high speed. . SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor memory circuit that does not malfunction even when operating voltage fluctuates due to changes in ambient temperature or variations in device manufacturing.

Another object of the present invention is to provide a semiconductor memory circuit that can speed up circuit operation by reducing the signal amplitude of a drive signal. The present invention will be specifically described below using examples and with reference to the drawings.

FIG. 5 shows a circuit diagram of one embodiment.

Note that the same elements as in FIG. 1 are indicated by the same symbols. Diodes D5 and D6 of memory cell 1 are composed of Schottky barrier diodes.

As shown in the figure, the write circuit 3 includes emitter-coupled transistors Q1 to O and collector resistors RO and Rl to R4.
, shot barriers connected between the connection point of the constant current source circuit 4 and the collector resistor R4 of the transistor Q2 and the ground potential terminal, and between the connection point of the collector resistors R1 and R5 of the transistor Q3 and the ground potential terminal, respectively. Transistor D
1, D2.

The constant current source circuit 4 includes a driving transistor α, its emitter resistor R5 and base bias resistor R6, a transistor D4, and a shot barrier transistor D3. The circuit elements constituting the circuit shown in FIG. 5 above are formed in semiconductor regions separated from the semiconductor substrate by Pn junctions on one semiconductor substrate by well-known semiconductor integrated circuit technology, although not particularly limited. be done.

In this case, each resistor, transistor, and diode are formed simultaneously. The diode D4 has a transistor structure in which the collector and base of the transistor are shorted. Therefore, even if variations in characteristics occur among individual elements, the relative variations between elements having the same configuration are small. For example, the base-emitter voltage ■BE(
Q4) and the forward voltage VBE (D4) of the diode D4, and the forward voltages of the diodes D1 to D3, D5, and D6 are approximately equal to each other. Further, the mutual resistance ratio of the resistors R1 to R hardly changes. As mentioned above, ■BE (Q4) of transistor 9 and diode D
Since VBE (D4) of 4 is almost the same, constant current circuit 4
, a voltage approximately equal to the forward voltage VBEl (D3) of the Schottky transistor D5 is applied across the resistor R5.

As a result, the collector current 1 of transistor Q is approximately
The value is BE(D3)/R5. Resistance R. The resistance value of is set at a ratio that is half of the resistance value of the resistance value. Resistance R1
and R2 are made equal to each other, and the current 1 causes these resistors and the resistor R to be equal to each other. The ratio is set such that the sum of the voltage drops occurring in the forward voltages of the shot barrier diodes Dl and D2 is equal to or larger than the forward voltage of the shot barrier diodes Dl and D2. Resistance R
The resistance values of R 3 and R 4 are made equal and are such that a current 1 causes a voltage drop of, for example, 200 to 300 m,V. The control signal V1 and input signals V2 and V3 applied to the write circuit 3 are not particularly limited, but are selected to have levels as shown in FIG. 7, for example.

Note that the transistors Q5 and q of the driver circuit 2 are provided corresponding to the transistor Qll for driving the word line X1 of the memory cell. transistor Q
ll and the base-emitter voltages of transistors Q5 and Q6 are equal, so the level of word drive signal ■X1 and node V
. l or V. 2 is equal to the difference between the level of the word line X1 and the level of the base potential (i) or (ii)W1.

The high level of the word drive signal
The negative value is approximately equal to or larger than half the forward voltage of . During each period of holding, reading, or writing information, the circuit shown in FIG. 5 performs the following operations.

Due to the high level of the one-hold period control signal V1, the transistor Q1 is turned on and the transistors Q2 and Q3 are turned off.

The resistor R is caused by the collector current of the transistor Q1 which is equal to the current 1 of the constant current circuit 4. A voltage drop of half the voltage across diode D3 occurs. At this time, the diodes Dl and D2 receive only half the above voltage and are in an off state. The voltage drop of the resistors R1 to R4 can be considered to be almost zero since the current is only the base current of the transistors Q5 and Q6. Therefore, node V. The voltage of l, VO2 is resistor R. approximately equal to the voltage drop. During this period, the potential of the word line X1 is 1-X1--BE (Qll), and the base potential is 2. Or ■W1 is resistance R. Since the voltage drop of is equal to 112VBE(D3), -112■BE(D
3) 1■BE (Q5) or -112■BE-■BE (D
3). The level of signal ■X1 is 112■I3E (D
5 or D6), and ■BE(Q5) and ■BE(Q
6) and VBE (Qll) are almost equal to each other, and the memory cell node ■. 0, ■.

Since the potential of the transistor Ql.1 is approximately equal to or lower than the potential of the word line X1, the potential of the transistor Ql. , Ql3's base potential VWO9■W1 is higher than the potential of the node ■CO9VC1.

Therefore, transistors Q9 and QlO of memory cell 1 are in an off state. The memory at this time is transistor Q7,
This is done by the operation of Q8. The base potentials ■WO and ■W1 of the transistors Ql2 and Ql3 of the drive circuit 2 during the two read periods are the same as the level during the above-mentioned holding period.

Since the word drive signal X1 becomes approximately O volts, the potentials VWO and VWl are lower than the potential of the word line X1.

The voltage drop will be lower. That is, the forward voltage .beta.BE(D3) of the diode D3 is lowered by half the value. If the transistor Q7 of the memory cell 1 is in the on state, the node ■ with respect to the potential of the word line X1. The potential of o is lower by the forward voltage ■BE (D5) of diode D5, and the potential of node V
The potential of Ol is approximately equal to the potential of word line X1. As a result, the base potential of transistor Q9 of memory cell 1 is 112
13. (D3), and the base potential of transistor QlO is 11 higher than the base potential of transistor Ql2.
2■B. (D3) lower. Due to this base potential relationship, the transistor Ql2 of the drive circuit is turned on, and the stored information in the memory cell 1 is detected as a voltage drop across the resistor RlO. Conversely, if transistor q is in the on state, stored information in memory cell 1 is detected as a voltage drop across resistor Rll.

In the circuit shown in Figure 5, shot barrier diodes D5 and D6
, D3 have the same configuration, and their characteristics, that is, the forward voltage, change in the same direction with respect to variations in the manufacturing conditions of semiconductor integrated circuits, and the resistors R5 and R.

As shown in FIG. 6, the ratio of the voltages to the Schottky barrier diodes D5 and D6 is exactly 2:1, so that the potentials VvvO and VWl of the drive circuit 2 are accurately adjusted to the node point, regardless of changes in the characteristics of the Schottky barrier diodes D5 and D6. ■. Potential of o and node VOl
is maintained at an intermediate potential between the potential of Therefore, there is no erroneous read operation.

During the third write period, the control signal V1 of the write circuit 3 is at a low level, and the transistor Q1 is in an off state.

Transistor Q2 or Q3 has a complementary input signal V
2, one of them is turned on by V3. When the input signal V3 is at a high level, the transistor 9 is turned on, and the current of the constant current circuit 4 flows to the transistor O. Due to the on state of the transistor Q3, the Schottky barrier diode D1 is forward biased, and the forward voltage ■
Since BO(D1) is generated, the node ■.

The voltage is 1BE(D1)-R3·I. Node■.
1 connects the voltage VBE (D1) with a resistor t/LRl and R.

The potential is the value divided by . With such a potential,
The base potential is relative to the potential of the word line X1.

is ■BE(D1)+R3・I
one! - becomes lower, and the base potential VWlRO+R1■8.

(D1) becomes lower. As a result, transistor q of memory cell 1 is turned off and transistor Q7 is turned on.

Since the forward voltage ■8E (D5) of the shot barrier diode D5 of the memory cell 1 and the forward voltage ■BE (D1) of the shot barrier diode of the write circuit 3 are almost equal, the levels of each part of the circuit at the time of writing described above are is as shown in Figure 8. During the above writing, the voltage drops of resistor R3 and resistor RO are exactly proportional to the forward voltages of diodes D3 and Dl, respectively, and
Since the mutual forward voltages of diodes D5 and D5 are almost equal, the levels in each part of the circuit shown in FIG.
It will change to an appropriate value depending on variations in the manufacturing process of D6 or changes in characteristics due to temperature changes.

Therefore, there are no erroneous write operations.

FIG. 9 shows a circuit of another embodiment replacing the constant current circuit of FIG. 5, in which the transistor Ql4
, a diode D7, and a resistor Rl4 are added.

The current 1 in this circuit is determined by the forward voltage of the shot barrier diode D3 as in FIG. In this circuit, the emitter of the transistor Ql4 exhibits an impedance sufficiently lower than the impedance of the bias circuit consisting of the resistor R6 and the diodes D5, D4, and D7 due to its amplification effect, so that the emitter of the transistor Ql4 is This reduces noise generated at the collector of Q4 from being added to its base via the collector-base capacitance.

As described above, in the semiconductor memory circuit of the present invention, manufacturing variations in the elements are canceled out by the circuit, and the operating margin is compensated for a wide range of temperature changes.

Therefore, it is possible to reduce the signal amplitude of the input signal for driving, and it is expected that the speed will be increased. The present invention is not limited to the above embodiments, and various modifications can be made. For example, in the above embodiment, the diodes D1 to
Although Schottky barrier diodes are used for D3, D5, and D6, they may all be ordinary diodes instead.

The present invention can be widely used as a semiconductor memory circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional semiconductor memory circuit, FIGS. 2 to 4 are timing charts thereof, FIG. 5 is a circuit diagram of a semiconductor memory circuit according to an embodiment of the present invention, and FIGS. FIG. 8 is a timing chart thereof, and FIG. 9 is a circuit diagram of another embodiment. 1...Memory cell, 2...Drive circuit, 3...
Write circuit, 4... Constant current source circuit, Q1 to Ql3.
...Transistor, D1-D3, D5, D6... Schottky barrier diode, D4... Diode, RO
, Rl~Rll, ROl9RC2DO resistance~IOC9l
ODl9ll29lOW9lORO, IOR...constant current source circuit.

Claims (1)

[Claims] 1. A memory cell including a pair of transistors whose collectors and bases are cross-coupled to each other, an element that generates a forward voltage that limits the potential of the collector of the transistor, and a memory cell that drives the memory cell. In the semiconductor memory circuit, the drive circuit includes first to third transistors whose emitters are commonly coupled, and a transistor coupled between the collector of the first transistor and one terminal of a power supply. second and third resistance means respectively coupled between a connection point between the collector of the first transistor and the resistance means and the second and third transistors; , comprising a constant current transistor coupled in series between the emitter of the common coupling and the other terminal of the power source and a fourth resistance means, and between the base of the constant current transistor and the other terminal of the power source. is an element that generates a forward voltage approximately equal to the base-emitter voltage of this transistor, and a forward voltage characteristic that is connected in series with this element and that is approximately equal to the forward voltage characteristic of the element in the memory cell. What is claimed is: 1. A semiconductor memory circuit characterized in that a bias circuit including an element and a bias circuit are combined. 2. The bias circuit includes a fourth transistor whose emitter is coupled to the base of the constant current transistor, and the series-coupled element is provided between the base and the other terminal of the power source. A semiconductor memory circuit according to claim 1, characterized in that: 3. The semiconductor memory circuit according to claim 1 or 2, wherein each of the transistors, the element for generating a forward voltage, and the resistance means are formed on the same semiconductor substrate.