JPS6042622B2 - Complementary MOS integrated circuit - Google Patents
Complementary MOS integrated circuitInfo
- Publication number
- JPS6042622B2 JPS6042622B2 JP52049214A JP4921477A JPS6042622B2 JP S6042622 B2 JPS6042622 B2 JP S6042622B2 JP 52049214 A JP52049214 A JP 52049214A JP 4921477 A JP4921477 A JP 4921477A JP S6042622 B2 JPS6042622 B2 JP S6042622B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- complementary mos
- mos integrated
- region
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、相補型ＭＯＳ集積回路（以下ＣＭＯＳＩＣ
と称す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS integrated circuit (hereinafter referred to as CMOSIC).
).
ＣＭＯＳＩＣでは、その動作中に、出力端子にインパ
ルス状の雑音が加わると、電源端子ＶＤＤ（！、Ｖ。。
との間に数ｍＡから数＋ｍＡの、異常な電流が定常的に
流れ、一度、電源を、切つてやらないと止まらない。こ
の現象をラッチアップ現象という。この異常電流は、電
池の寿命を短かくするのみならす、ＩＣ自体の永久的な
破壊をまねくこととなる。 第１図は、ＣＭＯＳの基本
的インバータの構造断面図である。In a CMOSIC, when impulse-like noise is applied to the output terminal during operation, the power supply terminal VDD (!, V...
An abnormal current of several mA to several + mA constantly flows between the power supply and the power supply, and it will not stop unless the power is turned off. This phenomenon is called latch-up phenomenon. This abnormal current not only shortens the life of the battery, but also permanently destroys the IC itself. FIG. 1 is a structural sectional view of a basic CMOS inverter.
図中、点線で示すように、この構造の中には、多くの寄
生素子がある。まず、ＮチャネルＭＯＳトランジスタの
ソース領域６またはドレイン領域７であるＮ゛領域、Ｐ
ウェル２、それにＮ型基板１によりＮ゛ＰＮの縦型バイ
ポーラトランジスタＴｌおよびＴ。を形成する。次に、
ＰチャネルＭＯＳトランジスタのソース領域８またはド
レイン領域９である Ｐ゛領域、Ｎ型基板１、及びＰウ
ェル２により、Ｐ゛ＮＰの横型バイポーラトランジスタ
Ｔ。およびＴ。を形成する。 さらに、各々のトランジ
スタのベースに直列にＰウェル２の抵抗成分による抵抗
、Ｒ、、Ｒ。There are many parasitic elements in this structure, as shown by dotted lines in the figure. First, the N' region, which is the source region 6 or the drain region 7 of the N-channel MOS transistor, and the P
The well 2 and the N-type substrate 1 form N゛PN vertical bipolar transistors Tl and T. form. next,
A P'NP lateral bipolar transistor T is formed by the P' region which is the source region 8 or drain region 9 of the P channel MOS transistor, the N type substrate 1, and the P well 2. and T. form. Furthermore, resistances R, , R due to the resistance components of P well 2 are connected in series to the base of each transistor.
及び、Ｎ型基板１の抵抗成分による抵抗Ｒ３、Ｒ、が形
成されている。 以上のような寄生素子が、原因になり
、インパルス状雑音が加われば、主として、トランジス
タＴｌ及びトランジスタＴ。が常時導通状態となり、定
常電流が流れる。従来この現象を、防止するためには、
トランジスタＴｌ及びトランジスタＴ４のベース幅を、
大きくとつて、トランジスタの電流増幅率を１以下にす
る方法、すなわち、Ｐウェル２の深さを大きくする、あ
るいは、図中のＷの値を大きくする、あるいはＰウェル
下にＰ゛の埋め込み層を設ける等の処置が考えられてい
た。 しかし、これらの方法は、チップサイズを増大さ
せ、また工程の複雑化を招いている。 本発明の目的は
、チップサイズを増大させることなく、また、何ら新ら
しい工程を追加することなくラッチアップを起こしにく
い相補型ＭＯＳ集積回路を提供することてある。Further, resistors R3 and R are formed by the resistance component of the N-type substrate 1. If the above-mentioned parasitic elements become a cause and impulse-like noise is added, it will mainly be caused by the transistors Tl and T. is always conductive, and a steady current flows. Conventionally, to prevent this phenomenon,
The base widths of transistor Tl and transistor T4 are
In other words, increase the depth of the P well 2, increase the value of W in the figure, or add a buried layer of P under the P well. Measures such as establishing a However, these methods increase the chip size and complicate the process. An object of the present invention is to provide a complementary MOS integrated circuit that is less prone to latch-up without increasing the chip size or adding any new processes.
次に本発明を実施例に従つて、図面を用いて、説明す
る。Next, the present invention will be explained according to examples and with reference to the drawings.
第２図ａおよびをは本発明の一実施例を示すそれぞれ
平面図およびＡ−Ａ’方向断面図である。Figures 2a and 2 are a plan view and a sectional view taken along the line AA', respectively, showing an embodiment of the present invention.
ＮチャネルＭＯＳのソース領域６の一部に島状のＰ゛領
域１１、１１′、・・・を、同様にＰチャネルＭＯＳの
ソース領域８の一部に島状のＮ゛領域１２、１２′、１
２″・・・をそれぞれ設け、それぞれソース電極１３ま
たは１４と接続してある。その他の点は従来のＣＭＯＳ
と同様てある。このようにすることにより、Ｎ型基板１
またはＰウェル２内でのポテンシャル分布が均一化され
るから、第１図に示した抵抗成分Ｒｌ，Ｒ２，Ｒ３およ
びＲ４は小さくなり、各寄生トランジスタＴｌ，Ｔ２，
Ｔ３およびＴ４のベース・工−ミッタ接合バイアスも少
さくなつて、各寄生トランジスタは遮断状態になつて寄
生効果は抑制される。Island-shaped P' regions 11, 11', . ,1
2"... are provided and connected to the source electrodes 13 or 14, respectively.Other points are conventional CMOS
It is similar to. By doing this, the N type substrate 1
Alternatively, since the potential distribution within the P-well 2 is made uniform, the resistance components Rl, R2, R3 and R4 shown in FIG. 1 become small, and each parasitic transistor Tl, T2,
The base-to-mitter junction bias of T3 and T4 is also reduced, each parasitic transistor is cut off, and parasitic effects are suppressed.
特に電流容量の大きな出力バッファ●トランジスタにお
いては、チャネル幅／チャネル長を大きくする必要があ
る関係上、非常に大きな効果がある。また、本発明を実
施するためには、従来のＣＭＯＳＩＣの工程以上に新た
に工程を追加する必要はないことは特に説明するまでも
ない。勿論Ｐチャネル側またはＮチャネル側のいずれか
一方のみに本発明を実施しても十分な効果がある。This is particularly effective for output buffer transistors with large current capacity, as the channel width/channel length must be increased. Further, it is needless to say that in order to carry out the present invention, there is no need to add any new process beyond the conventional CMOSIC process. Of course, sufficient effects can be obtained even if the present invention is implemented only on either the P channel side or the N channel side.
第１図は従来の相補型ＭＯＳインバータの構造断面図、
第２図ａおよびｂは本発明の一実施例である相補型ＭＯ
Ｓインバータのそれぞれ平面図およびＡ−Ｎ方向断面図
である。
１・・・・・Ｎ板基板、２・・・・・・Ｐウェル、３・
・・・・フィールド絶縁膜、４・・・・・・Ｎ＋導電型
領域、５・・・・・・Ｐ＋導電型領域、６・・・・・・
ＮチャネルＭＯＳのソース領域、７・・・・・・Ｎチャ
ネルＭＯＳのドレイン領域、８・・・・ＰチャネルＭＯ
Ｓのソース領域、９・・・・・・ＰチャネルＭＯＳのド
レイン領域、１０・・・・・・ゲート絶縁膜、１１，１
「・・・・・・島状のＰ＋領域、１２，１２″，１２″
・・・・島状のＮ＋領域、１３・・・・・・ソース電極
、１４・・・・・・ドレイン電極。Figure 1 is a cross-sectional view of the structure of a conventional complementary MOS inverter.
FIGS. 2a and 2b show a complementary MO which is an embodiment of the present invention.
FIG. 2 is a plan view and a cross-sectional view in the AN direction of the S inverter, respectively. 1...N plate substrate, 2...P well, 3...
...Field insulating film, 4...N+ conductivity type region, 5...P+ conductivity type region, 6...
Source region of N-channel MOS, 7... Drain region of N-channel MOS, 8... P-channel MO
Source region of S, 9... Drain region of P channel MOS, 10... Gate insulating film, 11, 1
"...Island-like P+ area, 12, 12", 12"
... Island-shaped N+ region, 13 ... Source electrode, 14 ... Drain electrode.
Claims (1)
ＭＯＳトランジスタを含む相補型ＭＯＳ集積回路におい
て、ソース領域の一部に、ソース領域とは導電型を異に
する領域を設けたＭＯＳトランジスタを含むことを特徴
とする相補型ＭＯＳ集積回路。1. A complementary MOS integrated circuit including a P-channel MOS transistor and an N-channel MOS transistor, which includes a MOS transistor in which a region having a conductivity type different from that of the source region is provided in a part of the source region. type MOS integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52049214A JPS6042622B2 (en) | 1977-04-27 | 1977-04-27 | Complementary MOS integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52049214A JPS6042622B2 (en) | 1977-04-27 | 1977-04-27 | Complementary MOS integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53133382A JPS53133382A (en) | 1978-11-21 |
| JPS6042622B2 true JPS6042622B2 (en) | 1985-09-24 |
Family
ID=12824709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52049214A Expired JPS6042622B2 (en) | 1977-04-27 | 1977-04-27 | Complementary MOS integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042622B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61150364A (en) * | 1984-12-25 | 1986-07-09 | Toshiba Corp | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211871A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor device |
-
1977
- 1977-04-27 JP JP52049214A patent/JPS6042622B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53133382A (en) | 1978-11-21 |
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