JPS6043038B2 - Manufacturing method of non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a rewritable non-volatile semiconductor memory (
EPROM) manufacturing method.

FIGS. 1a and 1b are a plan view and a sectional view taken along line A-A, showing the general structure of an EPROM. Here, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a floating gate, 5 is a polysilicon oxide film, and 6 is a control gate.

Next, this manufacturing process will be explained with reference to FIG.

First, a field oxide film 2 is formed on a P-type semiconductor substrate 1 by selective oxidation. Further, a gate oxide film 3 is formed and a first polysilicon film 4 is grown in a vapor phase (Fig. 2a).
. After diffusing impurities into the first polysilicon film 4 to give it conductivity, a photo-etching process (
The first polysilicon film 4 is processed by PEP (FIG. 2b).

Next, oxidation is performed to cover the polysilicon film 4 with an oxide film 5, and a second polysilicon film 6 is formed thereon, and by PEP,
The second polysilicon film 6 and the first polysilicon film 4 are processed using the same mask to form the control gate 6 and floating gate 4, resulting in the structure shown in FIG.

As shown in FIG. 1a, the floating gates 4, formed from a first layer of polysilicon, must be machined a distance 1 apart from each other. The distance 1 needs to be 4 μm or more in the current ultraviolet exposure and etching method. If the thickness is less than 4 μm, the separated polysilicon will short-circuit and insulation will not be maintained. In order to reduce the cell area and improve the degree of integration, it is required to reduce the distance 1 between floating gates, that is, the spacing between silicon patterns. An object of the present invention is to provide a method for manufacturing a highly integrated nonvolatile semiconductor memory.

According to the present invention, by performing the formation of the floating gate, that is, the vapor phase growth of polysilicon and the PEP twice in different directions, it is possible to reduce the spacing between the floating gates.

An embodiment of the present invention will be described below with reference to process diagrams shown in FIGS. 3a to 3e.

First, a field oxide film 2 is formed on a P-type substrate 1 by selective oxidation.

Furthermore, a gate oxide film 3 is formed, and a first polysilicon film 4 is grown in a vapor phase (FIG. 3a).

Then, impurities are diffused into the polysilicon film 4 to give it conductivity. Only the polysilicon portions that are to become floating gates constituting every other cell among the cells to be arranged in a matrix are left by PEP.

Using this polysilicon as a mask, a part of the gate oxide film 3 is removed (FIG. 3b). Oxidation is carried out again to form a gate oxide film 7 on the substrate 1, a polysilicon oxide film 8 on the polysilicon 4, and further grow a polysilicon film 9 thereon (FIG. 3c).

Here, impurities are diffused into the polysilicon film 9 to make it conductive. At the end, polysilicon 9 is left by PEP in the portion of the cell where the floating gate is not formed, and the other portions are removed. Gate oxide film 7 and polysilicon oxide film 8 are removed using polysilane 9 as a mask (FIG. 3d). In the steps shown in FIGS. 3C and 3D, adjacent floating gates 4 and 9 are insulated by polysilicon oxide film 8.

Moreover, since they are formed by separate PEP processes, short circuits cannot occur even if the distance between them is closer than the resolution accuracy of the resist. Even if the floating gates 4 and 9 overlap in plane due to misalignment of the masks, the polysilicon oxide film 8
It is insulated by -, so there is no short circuit. Therefore, according to the present invention, the space between the floating gates, which was conventionally required, is no longer necessary. Next, polysilicon 4 and 9 are oxidized to form polysilicon oxide film 5, and polysilicon 6 is further formed by vapor phase growth (FIG. 3e).

Furthermore, using the same mask, the polysilicon 4, 6, and 9 are processed, and the source and drain are further formed to obtain the final structure.The present invention described above eliminates the space between the floating gates that was previously required. is no longer necessary, improving the degree of integration. Furthermore, since the floating gates are formed by two steps of polysilicon growth and PEP, short circuits between adjacent floating gates are reduced. In the above-mentioned embodiment, the case with a control gate was explained, but an FA without a control gate
It can be applied to methods of manufacturing MOS memories and nonvolatile memories in which control gates and floating gates are not self-aligned.

Further, although in the above embodiment the floating gate 4 and the floating gate 9 do not overlap, the same effect can be obtained even if they overlap.

[Brief explanation of drawings]

Figures 1A and 1B are plan views and cross-sectional views showing the structure of a conventional memory cell, Figures 2A and 2B are manufacturing process diagrams, and Figures 3a-
e is a process sectional view showing one embodiment of the present invention. 1... Semiconductor substrate, 2... Field oxide film, 3, 7... Gate oxide film, 4, 9...
...Floating gate, 5,8...Polysilicon oxide film, 6...Control gate.

Claims (1)

[Claims] 1. In a method of forming a large number of memory elements having at least floating gates on the same semiconductor substrate, after forming the floating gates constituting the first group of memory elements and further forming an insulating film thereon, the second group of memory elements is formed. A method of manufacturing a nonvolatile semiconductor memory, which comprises forming a floating gate that constitutes a device.