JPS6043543B2 - Buffer memory diagnostic control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a buffer memory diagnostic control method, in particular, when there is an error in data read from the buffer memory, it is compared with normal data that has been block loaded from the main memory. In a data processing system that extracts a faulty storage element on a buffer memory, the above verification can be performed correctly even if there is an error in data that causes a line or cross on the buffer memory. The present invention relates to a buffer memory diagnostic control method that makes it possible to extract data corresponding to data in which an error has occurred from data that has been block loaded.

With recent advances in LSi technology, the storage capacity of buffer memories has been significantly increased.

Even when there is an error in read data due to a fixed fault in a storage element constituting a buffer memory, it is becoming difficult to determine which storage element has the fault. For this reason, there was an error 8
Extract bytes worth of data, and extract the correct 8 bytes of data corresponding to the 8 bytes of data with the above error from among the 64/byte worth of data that is block loaded from the main memory. It is considered to extract the faulty memory element by extracting the faulty memory element and comparing the two bits in correspondence with each other. In such a buffer memory diagnostic control method, if the 8 bytes of data with the above error do not cause a line cross on the buffer memory, the 8 bytes of data with the error are processed based on the address information of the 8 bytes of data with the error. Then, the block is loaded 64
It is relatively easy to extract the corresponding 8 bytes of data from the bytes of data. However, if a line cross occurs, it is necessary to take this into account when performing the above extraction. Note that, as will be described later in FIG. 4, line crossing means that, for example, the 6 sets of data loaded from the main memory start from the left end of the buffer memory as shown in FIG. 4. Instead of six segments (in this case, it can be placed one line above the buffer memory), six segments start from the middle position one line above the buffer memory, as shown by the diagonal line in Figure 4. I'm talking about what happens in such a case. When a line cross occurs in this way, the portion A in FIG. 4 loaded from the main memory is stored in the first line on the buffer memory, and the portion B in FIG. They are stored on a line, and the storage positions are on different lines. If such line crossings occur, it is necessary to take measures when comparing the above data to ensure that the comparison target does not differ from the one that should be compared. . The present invention is capable of performing desired extraction regardless of the presence or absence of line crossings by switching the determination mode of the extraction conditions for performing the above extraction depending on the presence or absence of the line crossings. It is an object.

Therefore, the buffer memory diagnostic control method of the present invention is a data processing system that transfers block-by-block data on the main memory to the buffer memory and proceeds with processing while accessing the data on the buffer memory. In the system, when an error is detected in a predetermined unit of data read from the buffer memory, the block-by-block data containing the predetermined unit of data is block-loaded from the main storage device, and then the error is detected. The predetermined unit of data having the error is compared with the corresponding normal predetermined unit of data loaded from the main storage device, and the faulty storage element on the buffer memory associated with the predetermined unit of data having the error is extracted. In a data processing system configured as such, an error address at which the predetermined unit of data having the error is read and a fetch address corresponding to the predetermined unit of data sequentially transferred from the main memory by block loading. In contrast, a logic circuit section configured to extract loaded correct data corresponding to the predetermined unit of data having an error is provided, and for the logic circuit section, the above predetermined unit of data is extracted. and line crossing instruction information indicating whether or not the predetermined unit of data to be compared is in a line crossing state on the buffer memory, The present invention is characterized in that the determination mode of the extraction condition is switched depending on the presence or absence of a cross state. This will be explained below with reference to the drawings.
FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram schematically representing the control according to the present invention in accordance with the flow of processing.

Also, Fig. 3 is an explanatory diagram showing the extraction conditions when no line crossing occurs, Fig. 4 is an explanatory diagram illustrating the mode when a line crossing occurs, and Fig. 5 is an explanatory diagram showing the extraction conditions when a line crossing occurs. An explanatory diagram showing the extraction conditions when In FIGS. 1 and 2, 1 is a buffer memory, 2 is a move-in register in which data loaded from the main memory (not shown) is set, for example, in units of 8 bytes, and 3 is a buffer memory. ●A memory read register in which 8-byte data read from buffer memory 1 is set; 4 is a bypass circuit; 5 is an error check circuit; 6 is an error data register; 3 is set one clock later and is held by the freeze signal (F or FREEZE) if it contains an error.
Reference numeral 7 denotes a normal data register, in which data that is block loaded from the main memory when the above error occurs is set sequentially in units of 8 bytes, and a normal data extraction signal (CS) is given. 8 is an error byte.
This is a register that is set to indicate in which byte of the 8 bytes the error exists when the above error occurs.

Reference numeral 9 is a first fetch address register, which sequentially loads address information for accessing memory 1 from the main memory by block loading in response to the occurrence of the above-mentioned error. 10 is a second fetch address register in which the contents of register 9 are set; 11 is a hold address register in which the contents of register 10 are set one clock later; What is set: 12 is the first adder, 13 is the error Address
This represents a register in which the absolute address within the buffer memory where an error occurred is set. Furthermore, 14 is a first length information register in which the byte length of the data to be loaded is set according to the address information set in the register 9, and 15 is a second length information register.
16 is a length information register in which the contents of register 14 are set, and 16 is a first line cross instruction information register in which information indicating this when a line cross occurs is set. , 17 is the second line crossing instruction information register; register 1
The contents of 6 represent what is set. 18 more
is the second adder, 19 is the addition result register, and 20 is the third adder.
an adder, 21 is a coincidence detection circuit, 22 is a logic circuit unit that generates a normal data extraction signal (CS), 2
3 represents a fourth adder, 24 represents a normal data extraction signal register, and 25 represents a byte instruction signal.

The operation will be explained below with reference to FIGS. 1 and 2.

(1) In normal processing, as is well known, the buffer
Processing is performed while accessing memory 1.

(2) In this case, the 8 read from buffer memory 1
The byte worth of data is set in the register 3 and checked by the error check circuit section 5 for the presence or absence of an error.

Then, one clock later, the above data is set in the register 6. (3) If an error exists, the error check circuit unit 5 issues a freeze signal F to fix the contents of the register 6.

On the other hand, which byte among the 8 bytes has an error is set in register 8 and fixed in the same manner. ) At this time, the address information has been transferred to the register 11, and the address information of the byte in which the error exists is extracted by the first adder 12 and set in the register 13.

The above processing up to (4) is the processing when an error exists in the data read from the buffer memory, and once it is confirmed that the error is a fixed fault error, the following processing operations are performed to extract the faulty storage element. to go into.

1) When the processing operation starts, data in blocks containing the 8 bytes of data that caused the error is loaded in blocks of 8 bytes from the main memory (not shown).

;) At this time, the start address of the data in the transfer unit is set in register 9, the byte length of the transfer unit is set in register 14, and if a line cross has occurred, that fact is set in register 16. .

Further, the transferred data is sequentially set in the register 7 via the register 2. 1) From the 64 bytes of data transferred by block load,
It is necessary to extract the timing at which data including the byte in which the error occurred was set in the register 7, fix the contents of the register 7, and compare it with the previously fixed contents of the register 6.

For this purpose, the illustrated logic circuit section 22 stores the address (ERROR) of the error byte held in the register 13.
-ADR) and the contents of register 9 (FET
(CH-ADR) and the contents (LENGTH) of the register 14 that are set sequentially, (FETCH-AD
R)≦(ERROR-ADR)≦(FETCH-ADR
)+(LENGTH)1
Check whether (1) is satisfied.

If it is satisfied, the correct data corresponding to the 8 bytes of data with an error held in register 6 is set in register 7, so a normal data extraction signal (CS) is generated. and register 7
The contents of the file should be fixed.

8) For this purpose, bits #26 to #31 in the contents of register 13 are subtracted by the same bits in the contents of register 9 by the second adder 18,
Set to 9.

And depending on the presence or absence of a carrier at that time (FET
Check the magnitude relationship between CH-ADR) and (ERROR-DR), and further add (FETCH-ADR) by the third adder.
Check the magnitude relationship between +(LENGTH) and (ERROR-ADR).

On the other hand, the coincidence detection circuit 21 checks whether a load corresponding to a line cross has been performed. (9) Line cross instruction information is further supplied to the logic circuit section 22,
It is detected whether the condition of the above equation (1) is satisfied. If you are satisfied, there is no line crossing.
A normal data extraction signal (CS) is generated and the contents of the register 7 are fixed. (1Q) Although not shown below, the contents of the register 6 and the contents of the register 7 are checked to find out which bit has an error, and the faulty storage element is extracted. [1] FIG. 3 shows the conditions for extracting the above signal (CS) when no line crossing occurs. In addition, in FIG. 3, for example, RLE″NGTH-
The reason why RcARRY(〉)J is written below the AJ column is that the carry (CARRY) is logical R.
This indicates that it will be lJ.

The illustrated case of RCARRY(<) may be considered similarly.
Furthermore, RA=(ERRORADR-FETCH, A
DR)J below the column RCARRYj(ku)J means (ERROR-ADR)ku(FETCH-ADR).
), and in that case, the carry (CARRY) becomes logical RO.

Note that the same applies to the case of FIG. 5, which will be described later.
(ERROR-ADR)-(FETCH-
(RETCH-ADR)>(ERROR
-ADR)4, the condition of equation (1) is not satisfied and the normal data extraction signal (CS) is not generated.

(r) A carry is generated in the second adder 18,
If there is a carry in the result of calculation in the third adder 20, the condition of equation (1) is satisfied, and a normal data extraction signal (CS) is generated.

(C) Furthermore, if a carry is generated in the second adder 18 and no carry is generated in the third adder 20, the condition of equation (1) is not satisfied, so the signal (C
S) does not occur.

[■] Figure 4 shows the situation when line crossing occurs, and one line (6 lines) on the buffer memory
An error has occurred in 8 bytes of read data where a line cross has occurred with respect to Applies to. In this case, since illustrated data A and data B are processed twice, data B
If an error occurs in the byte on the side, that is, if the access is made based on a line crossing, then the data should be satisfied, and as shown in FIG.
If there is a carry in the adder 18, the condition of equation (2) is not satisfied, and the logic circuit section 22 outputs the normal data extraction signal (
CS) does not occur.

(E) If no carry occurs in the second adder 18 and a carry occurs in the third adder 20, the condition of equation (2) is satisfied, and the normal data extraction signal ( CS) is generated.

(F) No carry occurs in the second adder 18 and no carry occurs in the third adder 20;
If the condition of equation (2) is not satisfied, the normal data extraction signal (C
S) does not occur.

Needless to say, CA), (B), in [1] above
Judgment mode of (C) and the above [old (D), (E
) and (F) are switched by supplying line cross instruction information to the logic circuit section 22 from the second line cross instruction information register 17 at the same timing. As explained above, according to the present invention, by providing the data byte length (LENGTH) and line crossing instruction information to the logic circuit unit 22, the same circuit Under this configuration, it becomes possible to generate a normal data extraction signal (CS).

Then, by the second adder 18. With the configuration in which the third adder 20 performs the calculation shown in FIG.

Incidentally, in order to generate the normal data extraction signal (CS), the condition that the coincidence detection circuit 21 in both FIGS. 3 and 5 is always ON is required.

This is because the above condition is a 64-byte internal condition (lower 6 bits of address bits 26 to 31), and the match detection circuit 21 detects a match of the upper 26 bits of address bits 0 to 25. be.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram diagrammatically representing the control according to the present invention in accordance with the flow of processing. Also, Fig. 3 is an explanatory diagram showing the extraction conditions when no line crossing occurs, Fig. 4 is an explanatory diagram illustrating the mode when a line crossing occurs, and Fig. 5 is an explanatory diagram showing the extraction conditions when a line crossing occurs. An explanatory diagram showing the extraction conditions when In the figure, 1 is a buffer memory, 5 is an error check circuit, 6 is an error data register, 7 is a normal data register, 8 is an error byte register, and 9 is a first fetch address register. , 13 is an error address register, 14 is a first length information register, 16 is a first line crossing instruction information register, 18
, 20 are adders, and 22 is a logic circuit section.

Claims (1)

[Claims] 1 Data in blocks on the main memory is buffered.
A data processing system that advances processing while accessing the data on the buffer memory, and when an error is detected in a predetermined unit of data read from the buffer memory. After loading a block of data containing the data from the main memory, the predetermined unit of data having the error is compared with the corresponding normal predetermined unit of data loaded from the main memory. , in a data processing system configured to extract a faulty storage element on the buffer memory associated with the predetermined unit of data having the error, an error address from which the predetermined unit of data having the error was read and the main memory; By comparing the fetch address corresponding to a predetermined unit of data sequentially transferred from the device by block loading, the correct loaded data corresponding to the predetermined unit of data containing the above error is extracted. a logic circuit section configured, and for the logic circuit section, the byte length information of the predetermined unit of data and the predetermined unit of data to be compared are in a line-cross state on the buffer memory. The buffer memory diagnostic control is configured to input line crossing instruction information indicating whether or not the line crossing condition is present, and the determination mode of the extraction condition is switched depending on the presence or absence of the line crossing condition. method.