JPS6043664B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to contact pads connected to conductive leads extending to contact selected semiconductor regions of semiconductor devices, particularly planar semiconductor devices.

The contact pad is connected to the lead-in conductor via a nail head bond that contacts the contact pad. Such a contact is known, for example, from 1 Solid State Electronics, 196th edition, Volume 8, pages 735-745. In such a semiconductor device, when a contact pad and a nail head bond are brought into contact with each other by an automatic contact connecting machine, the smaller the size of the contact pad, the more often errors in contact connection occur.

This is because the nail head bond cannot be centered on the contact pad with exact repeatability due to the inherent tolerances of the contact connector. However, in the case of a high frequency semiconductor device, there arises the disadvantage that the capacitance between the conductor lead to which the contact pad is connected and the semiconductor substrate region below the conductor lead increases and changes. This is because, in the event of an incorrect contact connection of the nail head bond, the capacitance of the overlapping portion of the nail head bond is added to the capacitance of the contact pad. Depending on the area of the overlap, the capacitance between the conductor lead connected to the contact pad and the substrate area below this conductor lead (in the case of a planar transistor, this substrate area becomes the collector area) increases. Change.

Therefore, in the case of high-frequency transistors, it is inevitable that
Variations and increases in capacitance to the collector area occur. A base region having an emitter region is formed in the collector region. Of course, the capacitance can be reduced by increasing the thickness of the oxide layer.

However, it can be manufactured by making the oxide layer thicker. Disadvantages arise in the process (longer oxidation time, stronger underetching required). And it is not possible to reduce the change in capacitance. On the other hand, these capacitance variations can be reduced by increasing the dimensions of the contact pad. But long! By doing so, the average capacity will increase. An object of the present invention is to reduce the capacitance introduced into the planar semiconductor device and to change the contact position of the nail head bond with respect to the contact pad when the nail head bond is brought into contact with the contact pad in mass production in the planar semiconductor device. The aim is to reduce fluctuations in installed capacity depending on

The present invention is applied to a semiconductor device having a first semiconductor device and at least one second semiconductor device forming a Pn junction with the first semiconductor device. A contact pad provided on an insulating layer provided on the first semiconductor region is provided on a second semiconductor region.
The contact pad is connected to a conductive lead extending over the insulating layer in contact with the semiconductor region of the contact pad, and a nail head bond is brought into contact with the contact pad. This semiconductor device includes a first semiconductor region having a first conductivity type, and a second conductive region provided in the first semiconductor region so as to form a Pn junction with the first semiconductor region. a second semiconductor region having a mold;
an insulating layer provided on the first semiconductor region, a contact pad provided on the insulating layer, one end of which extends over the insulating layer with one end in contact with the second semiconductor region, and the other end of which is in contact with the insulating layer; and a first conductor lead connected to the pad.

The contact pad includes a plurality of first pad pieces and a plurality of second pad pieces, and each of the second pad pieces is connected to the first conductor lead via a second conductor lead. , each of the first pad pieces being electrically isolated from each other and the second pad pieces and arranged to support a contacting nail head bond on the contact pad. Although the structure of the contact pad is different from that of the device of the present invention, the semiconductor device (
(This was conceived by the inventor of the present invention and is not publicly known) will be made easier to understand the semiconductor device of the present invention with reference to FIGS. 1 to 3.

FIG. 1 shows a cross section of a planar diode in which a p-type first semiconductor region 14 and an n-type second semiconductor region 13 form a Pn junction 15. The surface of this first semiconductor region 14 is covered by the oxide film 12. A contact pad 1 is provided on this oxide film 12 , one end of which is in contact with a second semiconductor region 13 and connected to the other end of a first conductor lead 4 extending over the oxide film 12 . Nail head bond 2 is in contact with this contact pad 1. When bringing the nail head bond 2 into contact with the contact pad 1,
During this contact operation, it is difficult to accurately contact and fix the nail head bond 2 at a predetermined position on the contact pad.

The above-mentioned problems occur particularly when the contact operation is carried out by an automatic contact connection machine. In order to minimize variations in the capacitance of the first conductor lead 4 with respect to the first semiconductor region 14 (semiconductor substrate), the contact portion of the nail head bond 2 is prevented from extending beyond the periphery of the contact pad 1. too,
The contact pad 1 must have certain minimum dimensions. In the simplest case, the object of the invention can be achieved by drilling a hole in the contact pad 1 within the area of the contact pad 1 required for contacting the nail head bond 2. FIGS. 2 and 3 show a top view of a planar transistor with perforated contact pads and a second
A cross-sectional view is shown along line A-A in the figure.

In FIG. 2, p
An n-type second semiconductor region 13 (base region) is formed in a first semiconductor region 14 (which is a semiconductor substrate and has a collector region). A p-type emitter region 16 is formed in this base region 13 by diffusion. An insulating layer 12 is provided on the surface of the collector region 14 . As shown in FIG. 3, the planar transistor includes a first perforated contact pad 1 (on the left side of the figure) and a second perforated contact pad 1' (on the right side of the figure).
Contains. Nail head bonds 2 are brought into contact with the first and second contact pads, respectively.
(see figure), but illustration of these nail head bonds is omitted to show the manufacturing stage. The free ends of the two first conductor leads 4 connected to the first contact pads 1 are in contact with the base area 13, and the holes 17 and the remaining parts are all connected. This remaining part contains the contact area 9. This contact area 9 is an area for temporary needle bond contact during measurement and marking of the individual planar transistors before dividing into individual planar transistors, and has the area necessary for this contact. The second contact pad 1' has the same structure as the first contact pad 1, but differs in the following points. i.e. the conductor lead 1 connected to the second contact pad 1''
8 adjoins the emitter region 16, and another conductor lead 19, also connected to the second contact pad 1'', extends onto an insulating layer (not shown).As shown in FIG.
An n-type third semiconductor region 6 is formed in the p-type first semiconductor region 14 (collector region) below the first contact pad 1.
is provided, and this region 6 is connected to the collector region 14 and P
An n-junction 8 is formed. This third region 6 is in contact with the free end of said conductor lead 19 connected to the second contact pad 1''. This third region 6 serves to achieve the object of the invention, but This is shown in German Patent Publication No. 1.
It is known from Seki No. 2927. In the planar transistor described with reference to FIGS. 2 and 3, the contact pad 1 is not covered by the nail head bond 2.
The capacitance of the part will be added to the capacitance between the base and collector of the planar transistor. For some reason, the part of contact pad 1 that is not covered by the nail head bond is the 1st part.
This is because it is electrically connected to the conductor lead 4 of.
This invention prevents the capacitance of the portion of the contact pad not covered by the nail head bond from being added to the capacitance between the base and collector.

An embodiment of the present invention will be described below with reference to FIG. FIG. 4 is a plan view of a planar transistor to which the present invention is applied, and differs from FIG. 3 only in the structure of the contact pad. Therefore, the structure other than the contact pad is the same as that shown in FIGS. 2 and 3, and therefore, explanations are omitted except for particularly necessary parts. In Figure 4, the first contact pad (on the left side of the diagram)
includes a plurality of first contact pad pieces 30 (six shown in the figure) and a plurality of second contact pad pieces 31 (two shown in the figure) in a first contact pad area. Contained within. This contact pad area includes the contact area 9 described in FIG.
It is in contact with 3. Each of the second contact pad pieces 30 is connected to the contact area 9 by a short second conductor lead 5. The nail head bond 2 (see FIG. 2) contacted on this first contact pad is not shown. However, the second contact pad piece 31 and the second
It is preferable that the direction in which the nail head bond is connected to the conductor lead 5 corresponds to the direction in which the nail head bond contacting the first contact pad is maximally deflected. The second contact pad (right side shown) has a plurality of first contact pad pieces 30 in its area.
(three shown in the figure) and a plurality of second contact pad pieces 31 (two shown in the figure). Second
Each of the contact pad pieces 31 is connected to the contact area 9 via a short second conductor lead 5, and the arrangement direction of the second contact pad pieces 31 and the second conductor lead 5 is a nail head bond. Similar to the first contact pad, the second contact position coincides with the maximum deflection direction. In the second contact pad, one end of the conductor lead 18 is connected to the contact area 9 and the other end is in contact with the emitter area 16. FIG. 4 shows that a third semiconductor region (corresponding to the semiconductor region 6 of FIG. 3) can be provided in the collector region 14 below the first contact pad and that this third semiconductor region 6 can be used as an emitter. It is clear that it can be connected to region 16 even if it is not specifically illustrated.

In FIG. 4, the nail head bond 2 brought into contact with the first contact pad area is deflected to the maximum and the contact area 9
Even if the nail head bond does not contact the second conductor lead 5 or the second contact pad piece 31,
The nail head bond 2 and the first conductor lead 4 are always electrically connected.

Also, if the nail head bond is deflected, it will be supported by one of the first contact pad pieces 30. Furthermore, the capacitance of the first pad piece 30 that is not covered by the nail head bond 2 is not added to the capacitance between the base and the collector. Therefore, the semiconductor device of the present invention shown in FIG.
The object of the present invention can be solved more effectively than the semiconductor device shown in the figure. The shapes of the first and second contact pad pieces are not limited to the illustrated shapes.

[Brief explanation of the drawing]

1 is a vertical cross-sectional view of a planar Pn diode with contact pads; FIG. 2 is a vertical cross-sectional view of a high-frequency planar transistor with perforated contact pads; FIG. 4 is a plan view of the planar transistor shown in the figure with nail bonds omitted, and FIG. 4 is a plan view of the planar transistor showing one embodiment of the present invention. 1... Contact pad, 2... Nail head bond, 4
...first conductor lead, 5...second conductor lead,
6... Third semiconductor region, 12... Insulating layer, 13...
・Second semiconductor region (or base region), 14...first
Semiconductor region (or collector region), 16... Emitter region, 30... First contact pad piece, 31... Second
contact pad piece.

Claims (1)

[Claims] 1. A first semiconductor region having a first conductivity type, and a second conductive region provided within the first semiconductor region so as to form a Pn junction with the first semiconductor region. a second semiconductor region having a mold, an insulating layer provided on the first semiconductor region, a contact pad provided on the insulating layer, one end of which is in contact with the second semiconductor region; In a semiconductor device having a first conductor lead extending over an insulating layer and having the other end connected to the contact pad, the contact pad includes a plurality of first pad pieces 30 and a plurality of second pad pieces 31. each of the second pad pieces is connected to the first conductor lead 4 via a second conductor lead 5, and each of the first pad pieces is connected to each other and the second A semiconductor device characterized in that the nail head bond 2 is electrically isolated from the pad piece and is arranged to support a nail head bond 2 that comes into contact with the contact pad. 2. The second pad piece 31 in Claim 1
2. The semiconductor device according to claim 1, wherein the second conductor leads 5 are arranged in a direction in which the contact position of the nail head bond 2 is maximally displaced. 3. The contact pad according to claim 1 is characterized in that it has a contact portion 9 which has a surface area sufficient to temporarily contact the needle bond and which is connected to the first conductor lead 4. A semiconductor device according to claim 1. 4. The semiconductor device according to claim 1 further includes an emitter region 16 provided in the second semiconductor region 13 of the second conductivity type, and an emitter region 16 provided in the second semiconductor region 13 of the second conductivity type, and a third semiconductor region 6 of a second conductivity type provided in the first semiconductor region 14; and the first and second contact pad pieces 30 connected to the emitter region 16 via a third conductor lead 18. , 31, and the third conductive lead 18 further includes the third contact pad.
2. The semiconductor device according to claim 1, wherein the first semiconductor region 14 forms a collector region and the second semiconductor region 13 forms a base region. .