JPS604404B2 - digital linearizer - Google Patents

Description

[Detailed description of the invention] When measuring temperature using a thermocouple, platinum resistance wire, etc.
For example, the thermoelectromotive force of a thermocouple exhibits nonlinearity with respect to temperature changes.

Therefore, when it is desired to directly read the temperature in degrees Celsius (or degrees Fahrenheit), it is necessary to linearize this nonlinearity by some method. The general method of linearization that has been considered in the past has been the polygonal line approximation method of an analog function generator configured with a feedback circuit using diodes.

However, the above-mentioned method has drift over time of diodes, amplifiers, etc., noise, and complexity of adjustment. Since the digital linearizer of the present invention performs nonlinear correction digitally, the above-mentioned drawbacks can be eliminated and highly accurate linearization can be performed.

The linearizer of the present invention uses the broken line approximation method,
For example, suppose there is a temperature-electromotive force curve as shown in FIG.

This curve is divided into n bending points (n=0, 1, 2...,
n) and (n11), which is approximated by the equation {1-. T=Af+A, (E-En)+C, ten (E
-ET2) 10C2 0...10An(E-ETn)+Cn...
… [1) A.

io: ET, SE issue:.

<E<ETIA,=0:E<ET,,ET2SE Evoice≧Poison;:ET・MiE<E～ C,=0:EkuBT,,ET2SE T,:ET,≦B<ET2 A2=0 : Eku ET2, ET3SE E voice wool also: E~miE<E~ C2=0:E<ET2,ET3SE T2:ET2SEkuET3 An=0:E<EM, (ETn+,)≦E Sound n: ETnmiE<kuEding…)Cn=.

:E<ETn, (ETn+・)≦ETn:BTn≦E<
(ETn+,) Here, T: temperature, E: thermoelectromotive force, E,
．． ~ETn: thermoelectromotive force at the bending point, Ao~An: slope of the broken line at each bending point, therefore, each bending point ET,, ET2,...
- If the slopes Ao, A, . . . An are generated and integrated for each ETn, the formula {1) can be obtained.

Next, in the above equation '1}, ET,,ET2,...E
If we replace Tn with a binary counter value, we get the following equation.

However, for convenience of explanation, each corner point will be divided into equal intervals of 2N. The situation is shown in FIG. T=poetry E+~
Correct 2 books < E3 2N + 2 as follows.

T=QP+Q2(E-1,2N)+C,10Q3(E-2
．． 2N)+C20・.・・・・・・・・・■Fold line constant, =0:ET, ≦E mother:.

E<1 is the line constant Q2 =0: E<102N, 2・2
NSE2・2N poisonous play;:・02N MiB<C,=
0: E<1・2N, 2・2NSE T,: 1・2NSE<2・2N Broken line constant Q3 FO: E<2・2N, 3・2NSE3‐
2N 3 Mitsuma ni harm: 2-2N MiE〈C2=0:E＜
212N, 3.2NSET2:2.2NSE<302N FIG. 1 is a schematic diagram of a digital linearizer, which is a basic element of the present invention.

In the figure, ◯ indicates a counter unit that converts thermoelectromotive force ETN into a digital quantity and stores a counter value corresponding to BTN, and D2 is a monitor counter unit configured on the same machine as D. D4 is a ROM (read-only memory unit) that stores a constant an necessary for the linearizer for each section;
3 is an address counter section for specifying the address of ROMD4, and D6 is a constant an read from ROMD4.
D7 is a parallel full adder, D5 adds its own output and the output of constant register D6,
This is a register section for temporarily storing the results. or,
D8 is an integration counter unit that receives the carry output from the parallel full adder D7, and G is a gate circuit for generating and stopping the clock necessary for calculation.The gate is opened with the start pulse to start calculation. The clock is sent to the address counter section D3, the register sections ○5 and D6, and the monitor counter section D2. After the calculation is completed, the matching circuit C
, the gate is disabled by the output from , and the clock is stopped. Next, the basic operation will be explained below.

It is assumed that the electromotive force BTN is stored in the counter D, and the register sections D5, D6, counter sections D3, D2, etc. have all been reset. To convert the electromotive force ETN into a digital quantity T, instead of comparing which number of the broken lines ETN corresponds to, the data EiN of the monitor counter section D2 is calculated starting from zero until EiN=ETN. to find the digital quantity T. The ROMD4 (read-only memory unit) stores differential values (referred to as line constants) ao, a, ... ai, ... an equivalent to each broken line, which are addressed and output by the address counter D3. get. Now, when the start pulse triggers the gate ○, the clock pulse advances the monitor counter section D2 one stage at a time, and the contents of D2 become ETN.
Perform calculations sequentially according to the above formula '2' until EiN=
When ETN is satisfied, the gate G is inhibited by the coincidence output of the coincidence circuit C, and the calculation is completed, and the digital quantity T is accumulated in the accumulation counter D8.

The calculation process is entrusted to the following. Both register parts D5 and D6 are N.
D7 is a parallel full adder consisting of N bits.

Further, the output carry is accumulated in the integration counter section D8. The value ai read out from the ROMD4 is now specified in the constant register section D6 in parallel binary code. Further, the register section D5 is reset in advance. Gate circuit G
, the contents of the constant register section D6 are added to the contents of the register section D5 by the parallel full adder ○7 and stored in D5 again. As a result, the added carry is accumulated in the cumulative counter section D8. However, since the register sections ○5 and D6 have only N bits, ai will be accumulated in the integration counter section D8 by adding 2N times. Therefore, by changing the polygonal line constant ai specified in the constant register section D6, any linear slope can be obtained, and the counter value corresponding to the electromotive force is 1.2N,
2・2N, ...m・2N for a・, a2, ...
. . , the Tn to be obtained can be found in the form accumulated in the integration counter section 08. Generalizing the above operation, it becomes as follows. Now, assume that the contents of register sections D5 and D6 are Cn and Fn, respectively.

Since the contents of constant register D6 are arithmetic constants ai, F
i=ai. Fi is a constant read from the constant register section D6, and is 1.2N, 2.2N within a certain broken line section.
Since it is constant, Fi=Fi-. Therefore, Fo=F,=...Fn=ai. Note that the initial condition is C
o=0, Fo=a; Contents Cn of register section D5
is represented by the following formulas, C,=C.

10FOC2=C, 10F, C3=C20F2 Cn=Cn-, 10Fn-, Adding the above Cn=nF.

...{31. '3}
If the formula is found and n=2N, register parts D5 and D6
The addition carry is Fo times, and Fo is accumulated in the integration counter Ds.

Next, one embodiment of the present invention will be specifically described. The digital linearizer of this embodiment is composed of, for example, 3 bits. The constant a, in the first interval is a, = 5 (101)
, the constant a2 in the second interval is set to a2=3(011). In the IJ set state before a clock is supplied through the gate circuit G, the register portion D5 is "000". Gate circuit ○. When the clock is supplied through the first period, a constant a, that is, "10" is stored in the constant register section D6.
1" is stored, and at the timing of the first clock, the constant register section D6 is set to "101" and the register section D5 is set to "101".
000'' are added by the parallel full adder D7, and the addition result is ``
101'' is stored in the register section D5. At the timing of the second clock, “10
1" and "101" of the register section D5 are added, and a carry "1" is output to the integration counter section 8, and
The addition result "010" is recorded in the register section D5. Thereafter, addition is performed in the same manner. The addition process in the first section is as follows.

Similarly, in the second section, a2=3, that is, "oll
'' is stored in the constant register section ○6, and the following additions are performed at the timing of the clock pulse.

In this way, in the addition process of 2N = evening = 8 times, the first
In the section, five carries are sequentially output, and in the second section, three carries are sequentially output, and these carries are integrated by the integration counter section D8.

FIG. 3 shows a timing chart in the above example,
FIG. 4 shows the relationship between the clock and the integrated carry value, in which the clock signal is sequentially counted by the monitor counter section D2 in response to the start signal, and the clock signal is counted sequentially by the monitor counter section D2. The integrated value of carry output until the clock pulse supply is stopped becomes a corrected output approximated by a polygonal line.

As described above, the present invention performs integration digitally, and high accuracy can be expected without having a large-scale arithmetic processing function as shown in equation '1'.

Furthermore, since it is a digital method, there is essentially no drift over time. Furthermore, by using a read-only memory, it has many advantages, such as being able to fully support IJ nearerizers for various thermocouples.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a digital linearizer in an embodiment of the present invention, FIG. 2 is a diagram explaining its principle, FIGS. 3 and 4 are diagrams explaining its operation, and FIG. It is a principle explanatory diagram. D,...Counter section, D2...Monitor counter section, D4
...ROM (read-only memory section), D5, D6
...Register section, D7...Parallel full adder, D8...
Integration counter section. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A read-only memory section in which a line constant a_i corresponding to each line is stored, and an address counter section that counts clock pulses during a gate time corresponding to an input predetermined digital amount and specifies the address of the read-only memory section. , an N-bit constant register section for storing the polygon constant a_i read from the read-only memory section, and a polygon constant a_i stored in this constant register section.
and a digital quantity stored in another N-bit register section at each clock pulse, and an N-bit full adder that adds the digital amount stored in another N-bit register section and stores the addition result in the other register section, and a carry output from this full adder. A digital linearizer consisting of an integration counter and an integration counter.