JPS6044667B2 - Output control method of data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling the output of patterns such as characters in a data processing system that outputs characters composed of dot patterns.

In a conventional POS terminal with a dot printer, one processor manages the entire system, and when printing out, this processor transfers one line of character information from memory to the dot printer according to a program. The dot printer control circuit converts the character code into a dot pattern using a decoder and a character generator and supplies it to the dot printer.

However, this type of POS terminal has the following problems: (1) It places a heavy load on the central processing unit, (2) It is very difficult to change the contents of the character generator according to the user's request, and (3) It requires a decoder and a character generator. Furthermore, because of the dedicated circuit configuration, the configuration of the printer control circuit becomes complicated and the cost is high, and it is impossible to print Kanji characters using just a two-character generator.

The present invention aims to eliminate the above-mentioned drawbacks, and provides an output control method for a data processing system, which has features such as the ability to easily change the type of printed characters, the configuration is simple, and the cost can be reduced. is intended to provide.

Therefore, the output control method of the data processing system of the present invention includes a main processor, a dot pattern output device, a slave processor that controls the dot pattern output device, and a shared memory connected to the main processor. and,
direct memory access means for accessing the shared memory by the slave processor, and the main processor is capable of writing a character dot pattern into a dot pattern storage area of the shared memory; When the pattern output device is desired to output a character string, the pattern output device is configured to write a string of character start addresses and predetermined activation contents to a buffer area of the shared memory, and then interrupt the slave processor, When the slave processor receives an interrupt from the main processor, the slave processor controls the direct memory access means to read the activation contents of the buffer area, and if the activation contents are predetermined, the slave processor controls the direct memory access means and reads the activation contents of the buffer area. controlling the means to sequentially read character start addresses in the buffer area; controlling the direct memory access means to read character dot patterns specified by the read character start addresses from the dot pattern storage area; The apparatus is characterized in that the read character dot pattern is supplied to the dot pattern output device. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram for explaining the main memory access of the slave processor, FIG. 3 is a diagram showing the print buffer and dot pattern storage area, and FIG. The figure shows the configuration of the character start address entry block, and Figure 5 is a diagram explaining the configuration of the print buffer when all characters in one line are lowercase letters and when all characters in one line are uppercase letters. FIG. 6 is a diagram showing an example of correspondence between print buffers and print digits.

In FIGS. 1 and 2, 1 is a main processor, 2 is a slave processor, 3 is a main memory, 4 is an inter-CPU interface, 5 is a DMA switching/parity check circuit, and 6 is an end. Notification circuit, 7 is RAr! 4 and 8 are ROM19-1 and 9
12 is a peripheral interface adapter, 10 is a timer,
Reference numeral 11 indicates a dot printer, 11a a driver/receiver, 11b a dot printer mechanism, and 12 an interrupt signal generation circuit. The main processor 1 performs various processes and controls other than dot printer control, and the slave processor 2 controls the dot printer 11. The main processor 1 and the slave processor 2 are, for example, IS-4B680s that operate with non-overlapping two-phase clocks φ1 and φ2.
0 (Fujitsu) type microprocessor can be used. The main processor 1 and the slave processor 2 perform synchronous operations with a phase shift of 112φ cycles. The main memory 3 is provided with not only a program storage area, a data storage area, and a work area of the main processor 1, but also a print buffer and a dot pattern storage area, which will be described later. CPU interface 4 is
Transferring the clock of main processor 1 to slave processor 2,
Transfer of reset signals from main processor 1 to slave processor 2, transfer of interrupt signals from main processor 1 to slave processor 2, and transfer of interrupt signals from slave processor 2 to master processor 1
This is used to transfer interrupt signals to, etc. The DMA switching and parity check circuit 5 performs bus disconnection and connection control between the main processor 1 and the main memory 3, bus disconnection and connection control between the slave processor 2 and the main memory 3, and parity check of address information and data. It is something. The end notification circuit 6 notifies the main processor 1 of the end of printing for one line.
There is something to notify you. RAM7 is slave processor 2
The ROM 8 is the working memory of the slave processor 2, and the ROM 8 is the program memory of the slave processor 2. The main processor 1 can read and write the main memory 3, but the slave processor 2 can only read the main memory 3. Before explaining FIG. 2, FIGS. 3 and 4 will be explained.

In Figure 3, 13 is the print buffer, 14 is the dot buffer, and 14 is the dot buffer.
In the pattern storage area, A indicates a start content entry block, B indicates a character start address entry block, and C indicates a dot-● pattern column element entry block. A print buffer 13 and a dot pattern storage area 14 are prepared in the main memory 3. Print buffer 13
is composed of RAM, and the dot pattern storage area 14 is composed of RAM or rewritable ROM. For example, lowercase alphanumeric kana characters are 7.
*9 dots are printed, and uppercase alphanumeric kana characters and kanji characters are printed with 7x18 dots. The dot pattern of alphanumeric and kana characters is stored in nine consecutive column element entry blocks C. In addition, column element entry block C
has an 8-bit configuration. When printing uppercase alphanumeric kana characters, the same column element is printed twice in succession. The dot pattern of kanji is 18 consecutive
Column elements are stored in the entry block C. In the start-up content entry block A of the print buffer 13, a start-up command for the slave processor 2, etc. is written. In the character start address entry block B, the start address of the column element entry block group in which the dot pattern of the character to be printed is entered, uppercase/lowercase character designation information, and kanji character designation information are entered, as shown in Figure 4. Ru. One character first address entry block B is assigned to lowercase letters, but two consecutive character first address entry blocks B are assigned to uppercase letters and kanji, and these blocks B are assigned the same first address. is entered. , FIG. 2 explains the main memory access of the slave processor 2.

After the main processor 1 writes the print start command and character information into the print buffer 13, it sends an interrupt signal to the slave processor 2. When the slave processor 2 receives this interrupt signal, it outputs address information specifying the activation content entry block A and a DMACS signal. The DMA switching/parity check circuit 5 sends the RREQ signal to the main processor 1 when the clock φ2 of the slave processor 2 becomes high level. When the main processor 1 receives the RREQ signal, it disconnects the address pattern and the data bus during the period when its own clock φ1 is at a high level (that is, the period when the clock φ2 of the slave processor 2 is at a high level), and at the same time disconnects the DMA signal. Output. Upon receiving the DMA signal, the DMA switching and parity check circuit 5 connects the slave processor 2 to the address bus and the data bus. As a result, when the clock φ2 of the slave processor 2 is at a high level, the contents of the activation content entry block A are taken into the slave processor 2. At this time, a data parity check is performed. When the clock φ2 of the slave processor 2 goes low, the slave processor 2 is disconnected from the address bus and the data bus, and the main processor 1 is disconnected from the address bus.
connected to the bus and data bus. Slave processor 2
reads the contents of the startup contents entry block and displays a dot.
Start the printer 11. When the dot printer 11 is activated and a character pulse interrupt occurs, the slave processor 2 writes the first character start address entry block B.
access. This access is performed in the same manner as the access to the activation content entry block A. When the slave processor 2 reads the contents of the character start address entry block B, it writes this into a column element address counter section (not shown) in the RAM 7. When a character pulse is followed by a dot pulse interrupt, slave processor 2 accesses column element C based on the contents of the column element address counter. It goes without saying that the read dot pattern is supplied to the dot printer 11. The contents of the element address counter in the above column are updated every one dot pulse for lowercase letters and Kanji characters, and every two dot pulses for uppercase letters other than Kanji characters. When nine dot pulses are generated, a second character pulse interrupt occurs and the second character start address entry block B is accessed.

If the contents of the first character start address entry block B and the contents of the second character start address entry block B are the same, the contents of the column element address counter will not be changed, and the contents of the column element address counter will not change. The contents are updated by dot pulses as described above.
When printing for one line is completed, the slave processor 2 sends an interrupt signal to the main processor 1, and at the same time sets end information in the end notification circuit 6.

When the main processor 1 receives the interrupt signal, it senses the contents of the completion notification circuit 6 and recognizes that printing for one line has been completed. Similar processing is performed when the slave processor 2 detects an error. FIG. 5 shows the structure of the print buffer when all characters on one line are lowercase letters and when all characters on one line are uppercase letters. Cll in Figure 5
R1 to CHR32 indicate printing characters, a downward arrow indicates forward printing, an upward arrow indicates reverse printing, and 1 to [Yes] indicate printing order. In this example, one line has 32 digits.
As can be seen from the figure, when all the characters in one line are lowercase, the first address entry block B is the character C.
The second character start address entry block B assigned to HRl is assigned to Bunnoji CHR2. below,
There is a similar one. If all letters on a line are in uppercase,
First and second character start address entry block B
is assigned to the character ClIRl, and the third and fourth character start address entry blocks are assigned to the character CHRl.

The same applies hereafter. As can be seen from FIG. 5, the system of FIG. 1 is capable of reciprocating printing. FIG. 6 shows the correspondence between print buffers and print digits.

As can be seen from FIG. 6, there is a one-to-one correspondence between the character start address entry block B and the printing digits, and uppercase letters (including Kanji characters) are printed in an area corresponding to two digits. As is clear from the above description, according to the present invention, the type and font of characters in the dot pattern storage area can be changed freely by IPL etc., and the configuration of the control unit of the character output device can be simplified. Also, effects such as significantly reducing manufacturing costs can be obtained.

It should be noted that the present invention is not limited to the above-mentioned embodiment, but it is clear that it can be realized in a similar manner when the number of dots forming one character is large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram for explaining main memory access of a slave processor, FIG. 3 is a diagram showing a print buffer and dot pattern storage area, and FIG. The figure shows the configuration of the character start address entry block, Figure 5 shows the configuration of the print buffer when all characters on one line are lowercase letters and when all the characters on one line are uppercase letters, and Figure 6 shows the configuration of the print buffer when all characters on one line are uppercase letters. FIG. 2 is a diagram showing an example of correspondence between print buffers and print digits. 1... Main processor, 2... Slave processor, 3... Main memory, 4... Inter-CPU Iwata interface, 5... DMA switching and parity
Check circuit, 6... Completion notification circuit, 7...
・RAMl8...ROMl9-1 and 9-2...
...Peripheral interface ●Adapter, 10...
・Timer, 11... Dot printer, 12.
. . . Interrupt signal generation circuit, 13 . . . Print buffer, 14 . . . Dot pattern storage area.

Claims (1)

[Claims] 1 a main processor, a dot pattern output device, and a slave processor that controls the dot pattern output device;
The main processor comprises a shared memory connected to the main processor, and direct memory access means for accessing the shared memory by the slave processor, and the main processor stores characters in a dot pattern storage area of the shared memory. If you want to write a dot pattern and have the dot pattern output device output a character string, write a string of character start addresses and predetermined startup contents to the buffer area of the shared memory, and then write the string to the slave processor. When the slave processor receives an interrupt from the main processor, the slave processor controls the direct memory access means to read the activation contents of the buffer area, and makes sure that the activation contents are a predetermined one. If it is, the direct memory access means is controlled to read the character start addresses in the buffer area in order, and the direct memory access means is read out in order.
The character dot pattern specified by the read character start address is read from the dot pattern storage area by controlling the access means, and the read character dot pattern is supplied to the dot pattern output device. Output control method for data processing systems.