JPS6044850B2 - Frequency converter gain control circuit - Google Patents
Frequency converter gain control circuitInfo
- Publication number
- JPS6044850B2 JPS6044850B2 JP6571577A JP6571577A JPS6044850B2 JP S6044850 B2 JPS6044850 B2 JP S6044850B2 JP 6571577 A JP6571577 A JP 6571577A JP 6571577 A JP6571577 A JP 6571577A JP S6044850 B2 JPS6044850 B2 JP S6044850B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency converter
- control circuit
- gain control
- gain
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims 1
- 101150073536 FET3 gene Proteins 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- HXJKWPGVENNMCC-UHFFFAOYSA-N 2,5-Dimethoxy-4-ethylamphetamine Chemical compound CCC1=CC(OC)=C(CC(C)N)C=C1OC HXJKWPGVENNMCC-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
Description
【発明の詳細な説明】
本発明はFM受信機用フロントエンド、TV用VHF
チューナ等において、温度変化による利得変動を補償し
た周波数変換器の利得制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention is a front end for an FM receiver, a VHF for TV.
The present invention relates to a gain control circuit for a frequency converter that compensates for gain fluctuations due to temperature changes in tuners and the like.
一般に周波数変換器内の半導体増幅素子はゲインをか
せげる様なバイアス条件となつており、その結果温度に
対して利得の変動が生ずる。Generally, a semiconductor amplifying element in a frequency converter is biased to increase its gain, and as a result, the gain fluctuates with temperature.
その為従来、第1図に示される回路構成によりその利得
変動に対する補償をしていた。 即ち、第1図はFM受
信機のフロントエンドの回路ブロックで、1は高周波増
幅器、2は局部発信器、3はデュアルゲートのドET(
電界効果トランジスタ)で、このFET3は周波数変換
器の変換増幅素子として用いられる。Conventionally, therefore, compensation for the gain fluctuation has been made using the circuit configuration shown in FIG. That is, Fig. 1 shows the front-end circuit block of an FM receiver, where 1 is a high frequency amplifier, 2 is a local oscillator, and 3 is a dual-gate DOET (
This FET 3 is used as a conversion amplification element of a frequency converter.
そしてこのFET3のゲートはそれぞれ高周波増幅器1
及び局部発信器2の出力に接続されている。FET3の
ドレインはIF増幅器4に接続され、そのソー スはバ
イパスコンデンサCl、サーミスタ5、ソース抵抗R、
の並列接続を介して接地される。又、R29R3はバイ
アス抵抗、C2はバイパスコンデンサである。 かくの
如き回路構成において、その動作を説明すると、入力電
波は高周波増幅器1にてコイルレとコンデンサCsで決
まる共振周波数と一致した時選択増幅され、周波数変換
器を構成するFET3のゲートに印加されると共に局部
発振回路2の出力もFET3の別のゲートに印加され、
互に混合され、そのヒート出力周波数は中間周波数出力
となつてIF増幅器4に印加される。The gate of this FET3 is connected to the high frequency amplifier 1.
and the output of the local oscillator 2. The drain of FET3 is connected to IF amplifier 4, and its source is connected to bypass capacitor Cl, thermistor 5, source resistor R,
grounded through a parallel connection of Further, R29R3 is a bias resistor, and C2 is a bypass capacitor. To explain the operation of such a circuit configuration, the input radio wave is selectively amplified by the high frequency amplifier 1 when it matches the resonance frequency determined by the coil relay and the capacitor Cs, and is applied to the gate of the FET 3 that constitutes the frequency converter. At the same time, the output of the local oscillation circuit 2 is also applied to another gate of the FET 3,
The heat output frequencies are mixed together and applied to the IF amplifier 4 as an intermediate frequency output.
又、FET3のソースはバイパスコンデンサClにより
、少なくとも中間周波数以上の周波数に対しては接地さ
れたと等しくなり、FET3はソース接地周波数変換増
幅器としてその変換利得を有する。そして温度が変動す
ると、FET3のバイアスが変動し利得変動を起すのを
防止する為に設けられたサーミスタ5の内部インピーダ
ンスが変動・して、ソース直流電位が変動し、FET3
のソースとゲート間のバイアスが変動するのを防止する
様に働らく。しカルながらこの様にバイアス変動が少な
くなる様な利得制御方法では、バイアス条件がむずカル
くなるばかりでなく、高周周波増幅、器1の出力に接続
されるゲートに直流バイアスを与える為に設けたバイパ
スコンデンサCoが高周波増幅器1内のLC共振回路と
直列接続されているため、このコンデンサC2に高周波
において、インダクタンス分が少なく、高周波特性の非
常によいものが要求される等の欠点を有していた。そこ
で本発明は上記欠点を除去する為になされたもので、周
波数変換器の温度変化による利得変動をバイアスの変動
を押える事により防止するのではなく、ソースインピー
ダンスを温度変化に従つて変化させ補償しようとするも
のである。以下、第2図を用いて本発明を詳細に説明す
る。高周波増幅器1の出力はカツプリングコンデンサC
4を介してFET3のゲートに印加される。Further, the source of the FET 3 is grounded by the bypass capacitor Cl at least for frequencies higher than the intermediate frequency, and the FET 3 has a conversion gain as a source-grounded frequency conversion amplifier. When the temperature fluctuates, the internal impedance of the thermistor 5, which is provided to prevent the FET 3 bias from fluctuating and gain fluctuations, fluctuates, causing the source DC potential to fluctuate, causing the FET 3 bias to fluctuate.
It works to prevent the bias between the source and gate of the circuit from changing. However, such a gain control method that reduces bias fluctuations not only makes the bias conditions difficult, but also makes it difficult to apply DC bias to the gate connected to the output of high-frequency amplification device 1. Since the provided bypass capacitor Co is connected in series with the LC resonant circuit in the high frequency amplifier 1, this capacitor C2 has drawbacks such as requiring a capacitor C2 with low inductance and very good high frequency characteristics at high frequencies. Was. Therefore, the present invention was made to eliminate the above-mentioned drawbacks. Instead of preventing gain fluctuations due to temperature changes in the frequency converter by suppressing bias fluctuations, the present invention compensates for them by changing the source impedance according to temperature changes. This is what I am trying to do. Hereinafter, the present invention will be explained in detail using FIG. 2. The output of high frequency amplifier 1 is a coupling capacitor C
4 to the gate of FET3.
ゲートとアース間にはバイアス抵抗R4が接続されてい
る。又、FET3のソースはソース抵抗R1と並列に接
続された、バイパスコンデンサC1とサーミスタ5でな
る直列回路を介して接地される。かくの如き回路構成に
より、サーミスタ5は電流帰還抵抗として動作し、ソー
スインピーダンスは、ソース抵拍只,とサーミスタ5の
インピーダンスとの並列インピーダンスに成る。そして
温度が変動するとFET3のバイアス値が変動すると共
にサーミスタ5の内部インピーダンスも変動し、その結
果ソースインピーダンスも変動し利得が変動するのを防
止する。例えば温度が上昇した時、FET3のバイアス
一の変動により利得が減少する様なバイアス設定がされ
ている場合、負の温度係数を有するサーミスタ5を用い
ればソースインピーダンスを減少させ、結果的に利得の
変動は防止される。A bias resistor R4 is connected between the gate and ground. Further, the source of the FET 3 is grounded via a series circuit consisting of a bypass capacitor C1 and a thermistor 5, which are connected in parallel with the source resistor R1. With such a circuit configuration, the thermistor 5 operates as a current feedback resistor, and the source impedance becomes a parallel impedance of the source resistor and the impedance of the thermistor 5. When the temperature changes, the bias value of the FET 3 changes, and the internal impedance of the thermistor 5 also changes. As a result, the source impedance also changes, which prevents the gain from changing. For example, if the bias setting is such that the gain decreases due to fluctuations in the bias of FET 3 when the temperature rises, using the thermistor 5 with a negative temperature coefficient will reduce the source impedance, resulting in a decrease in the gain. Fluctuations are prevented.
FET3のバイア又設定条件によつては温度が上昇する
と利得が増加する様に設計されているならば、正の温度
係数を有するサーミスタ5を用いればその目的を達成す
る事ができる。尚、本発明の実施例ではFETを用いて
説明し−たが、通常のトランジスタでもよく、その場合
エミツタがFETのソースに対応する。If the gain is designed to increase as the temperature increases depending on the vias or setting conditions of the FET 3, the purpose can be achieved by using the thermistor 5 having a positive temperature coefficient. Although the embodiments of the present invention have been described using FETs, ordinary transistors may also be used, in which case the emitter corresponds to the source of the FET.
以上、説明した様に本発明は、温度変化に対し利得の変
動を補償するためにソースインピーダンスを温度変化に
従つて変動させる様にしたから、従来のようにバイアス
値が温度変化に対して変動しない様にしたものより回路
構成が簡単となり、設計も容易となりコストダウンにも
つながる等工業上その効果は頗る大なるものである。As explained above, in the present invention, the source impedance is changed according to temperature changes in order to compensate for gain fluctuations due to temperature changes. This has great industrial effects, such as the circuit configuration being simpler than the one in which it is not used, design is easier, and costs are reduced.
第1図は従来のFM受信機のフロントエンド回路図、第
2図は本発明の一実施例のFM受信機のフロントエンド
回路図である。
1・・・・・・高周波増幅器、2・・・・・・局部発振
器、3・・・・・・FETl4・・・・司F増幅器、5
・・・・・・サーミスタ。FIG. 1 is a front-end circuit diagram of a conventional FM receiver, and FIG. 2 is a front-end circuit diagram of an FM receiver according to an embodiment of the present invention. 1...High frequency amplifier, 2...Local oscillator, 3...FET14...F amplifier, 5
...Thermistor.
Claims (1)
バイパスコンデンサとサーミスタの直列回路を接続し、
温度変化による利得変動を補償するようにした事を特徴
とする周波数変換器の利得制御回路。 2 周波数変換用トランジスタへFET(電界効果トラ
ンジスタ)より成る特許請求の範囲第1項記載の周波数
変換器の利得制御回路。[Claims] 1. A series circuit of a bypass capacitor and a thermistor is connected in parallel to the emitter resistor of a frequency conversion transistor,
A gain control circuit for a frequency converter, characterized in that it compensates for gain fluctuations due to temperature changes. 2. A gain control circuit for a frequency converter according to claim 1, wherein the frequency conversion transistor is an FET (field effect transistor).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6571577A JPS6044850B2 (en) | 1977-06-06 | 1977-06-06 | Frequency converter gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6571577A JPS6044850B2 (en) | 1977-06-06 | 1977-06-06 | Frequency converter gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54806A JPS54806A (en) | 1979-01-06 |
| JPS6044850B2 true JPS6044850B2 (en) | 1985-10-05 |
Family
ID=13294985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6571577A Expired JPS6044850B2 (en) | 1977-06-06 | 1977-06-06 | Frequency converter gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6044850B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633841U (en) * | 1979-08-22 | 1981-04-02 | ||
| JPS63102316U (en) * | 1986-12-23 | 1988-07-04 |
-
1977
- 1977-06-06 JP JP6571577A patent/JPS6044850B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54806A (en) | 1979-01-06 |
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