JPS6044868B2 - sampling pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for generating control signals for driving a matrix addressing television.

Matrix address televisions that use gas discharge elements (plasma), electroluminescent elements (EL), liquid crystals, etc.
It has been actively researched in recent years.

FIG. 1 shows a block diagram of a liquid crystal television.

The television broadcast wave received by the tuner 1 is amplified by the video intermediate frequency amplification circuit 2, and the audio component is amplified by the audio amplification circuit 3 and then drives a speaker.

The output of 2 is amplified by the video amplification circuit 4, and the AID
applied to converter 5.

The output of 4 is applied to a control signal generation circuit 6.

At step 6, a vertical synchronization signal and a horizontal synchronization signal are separated from the composite video signal to generate various control signals and various clock pulses for controlling the entire liquid crystal television.

The output of the AID converter 5 is written into the line memory 7, transferred to the line memory 8, and applied to the liquid crystal matrix panel 10 via the signal electrode drive circuit 9. The ten scanning lines are line-sequentially scanned by a scanning electrode drive circuit 11.

FIG. 2 is a simplified timing chart of the liquid crystal television shown in FIG.

SV is a vertical synchronization signal, Vg is a video signal, SH is a horizontal synchronization signal, φ is a sampling pulse, and MT is a memory transfer pulse. During the period of SH■0, a sampling pulse φ is generated, and the output of the AID converter is written into the line memory 7 by this sampling pulse φ. The signal written in 7 during period a is the first memory transfer pulse MT.
The signal is transferred to the line memory 8 and applied to the liquid crystal matrix panel 10 via the drive circuit 9. During this time 7
Signals are written in the next period. The signal written in 7 during the period is transferred to 8 by the second memory transfer pulse MT. The same operation is repeated below. FIG. 3 is a diagram showing the principle of a panel called a double matrix panel, which was devised to improve image quality by increasing the time during which signals are applied to pixels on a liquid crystal panel.

This will be explained below using FIG. Several layers of thick lower glass 1
2, a thin metal electrode 15 and a transparent electrode 16 are formed on the upper glass plate 14, and the transparent electrode 13 on the lower glass plate 12 and the metal electrode 15 on the upper glass plate 14 are orthogonal to each other. They are overlapped and bonded via a spacer 17 having a thickness of 10 μm to several + μm. A gap 18 between two glass plates 12 and 14 is filled with liquid crystal.

The electrodes 15 are connected to the A system (A1 to A4) and the B system (B1 to B4).
) is divided into two parts. Reference numerals 19 and 20 denote signal electrode drive circuits for driving the electrodes 15, which are expressed by integrating the line memory 7, the line memory 8, and the drive circuit.

13 is a scanning electrode, and 15 is a signal electrode.

When a scanning signal is applied to C1 and signals are applied to A1 to A4 and B1 to B, the pixel on the C1 electrode (the intersection of the C1 electrode and 16) changes the brightness according to the applied signal. Third
Although the figure shows an example in which there are two scanning electrodes 13 and four signal electrodes 15 in both the A system and the B system, generally both 13 and 15 are constructed with a larger number of electrodes.

FIG. 4 is a timing chart when driving the dual matrix liquid crystal panel shown in FIG. 3.

SV is a vertical synchronizing pulse, SH is a horizontal synchronizing pulse, φ9 is a sampling pulse for writing the output of the AID converter 5 to the memory 7 of the A system, and φB is the output of the AID converter 5 to the memory 7 of the B system Sampling pulse for writing, MT transfers the contents of memory 7 to memory 8.
This is a memory transfer pulse for transferring to. The explanation will be given below using FIG. 4. The output of the AID converter 5 is written into the memory 7 of the A system at φe, and is written into the memory 7 of the B system at φ8.

The signal written to the memory 7 during period a is changed to A by MT.
Both the system and the B system are simultaneously transferred to the memory 8 and applied to the liquid crystal panel for a period b. Similarly, the signal written in the memory 7 during period b is transferred to the memory 8 by the MT,
It is applied to the liquid crystal panel during period C. Therefore, in order to drive a double matrix liquid crystal panel, two systems of sampling pulses φA and φB are required. An object of the present invention is to provide a sampling pulse generator capable of generating various types of sampling pulses for driving a liquid crystal matrix panel of a device that performs television display using a liquid crystal matrix panel with a relatively simple circuit configuration. There is a particular thing.

The present invention includes an N-bit shift register, N AND gates, a circuit for generating a reference sampling pulse, a pair of NAND gates, one NOT gate, and one zero
The N-bit shift register uses a horizontal synchronization signal as a clock signal;
The vertical synchronization signal is used as a clear signal, and the result of a logical operation performed by the logic circuit on the vertical synchronization signal and the output signal of the shift register itself is used as an input signal, and the N-bit output signal of the shift register and the reference sampling pulse are used as input signals. are logically ANDed by the N AND gates, respectively, and N types of sampling pulses are output.

FIG. 5 shows a first embodiment of generating sampling pulses φA and φB according to the present invention.

FIG. 6 is a timing chart of the device shown in FIG. The apparatus shown in FIG. 5 will be explained below. 21 and 22 are N
23 is an 0R gate, 24 is a shift register, 25 is a NOT gate, 26 is a reference sampling pulse generator, and 27 and 28 are N1 gates.

When the output is 0, the shift register 24 is cleared, so both the first bit output S1 and the second bit output are 0.

At this time, the output of the NAND gate 21 is 1.
The output of 21 passes through an 0R gate 23 and is applied to the input h of 24.

26 produces an output pulse φ only when SH=0.

Therefore, when mowing=o, the outputs φA and φB of the AND gates 27 and 28 are not generated. When mowing=1, the clock pulse SH applied to 24 causes 24 to start operating, and S1=1. At the same time, the signal S1 is output to the NOr gate 25
It passes through and is applied to 22, and the output of 21 returns to 0. 2
Due to the first clock pulse SH, S2 becomes 1, and S
1 returns to O.

is fed back to the input h of 24, so S1=1 and S2=0 by the third clock pulse. Thereafter, similar operations are repeated to obtain the signals Sl and S2 shown in FIG. Here, perform the following logical AND operation
By using the D gates 27 and 28, two types of clock pulses φ9 and φ8 can be obtained. The dual matrix liquid crystal panel shown in FIG. 3 can be expanded to a multiple matrix liquid crystal panel.

In the case of a multi-matrix liquid crystal panel, even more sampling pulses as shown in FIG. 4 or FIG. 6 are required. The sampling pulse generator according to the present invention can be easily extended to drive multiple matrix liquid crystal panels. FIG. 7 shows a second embodiment in which a triple matrix liquid crystal panel is driven. FIG. 8 is a timing chart of the device shown in FIG. In FIG. 7, the shift register 29 is increased by 1 bit compared to FIG. 5, and the AND
One gate 30 is added. Sampling pulses φA and φIφ shown in FIG. can be obtained by performing a logical AND operation as shown in the following equation. Generally, when driving an N-layer matrix liquid crystal panel, an N-bit shift register is used as the shift register 24 shown in FIG. The circuit configuration except for the gate is exactly the same.

However, the input to the 0R gate 23 becomes the output of the NAND gate 21 and the N-th output of the shift register. The present invention provides means for generating sampling pulses for driving a dual matrix liquid crystal panel, and has a relatively simple circuit configuration.

It can be easily expanded to drive multiple matrix liquid crystal panels.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall operation of a liquid crystal television, FIG. 2 is a timing chart showing the operation of a liquid crystal television, and FIG. 3 is a diagram showing an example of a double matrix liquid crystal panel.
FIG. 4 is a diagram showing a timing chart for driving a double matrix liquid crystal panel, FIG. 5 is a diagram showing a first embodiment of a sampling pulse generator for driving a double matrix liquid crystal panel according to the present invention, and FIG. 5 is a timing chart showing the waveforms of each part of the device shown in FIG. 5, FIG. 7 is a diagram showing a second embodiment of the sampling pulse generator for driving a triple matrix liquid crystal panel according to the present invention, and FIG. Each part of the device shown in Figure 7. This is a timing chart showing the waveform of . 21, 22... NAND gate, 23... 0R gate, 24... shift register, 25... NOT gate, 26... reference sampling pulse generator, 27,
28, 30...AND gate.

Claims (1)

[Claims] 1 In a device that generates N types of sampling pulses to drive a liquid crystal matrix panel of a device that performs television display using an N-multiplexed liquid crystal matrix panel; N which operates as a ring counter by using the synchronization signal as a clock pulse and applying the output of the 2-input OR gate described later.
a bit shift register; a logic circuit having a function of becoming 1 when an inverted signal of a vertical synchronization signal is applied and returning to 0 when the output of the first bit of the shift register becomes 1; and an output of the logic circuit; a two-input OR gate that takes the output of the N-th bit of the shift register as two inputs and applies the output as an input to the shift register; a circuit that generates a reference sampling pulse; A sampling pulse generator comprising N two-input AND gates having the reference sampling pulse as a common input and outputting N types of sampling pulses.