JPS604488B2 - Microprocessor CPU reset method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to ensuring that a CPU is reset when power is turned on in a terminal device using a microprocessor.

In recent years, technological advances in microprocessors have been remarkable, and there are increasing attempts to use them in data communication and telephone terminal devices to improve functionality and make operations more convenient.

These terminal devices are generally located at a location remote from the center convector or telephone exchange, and are often operated by ordinary users who are not specially trained.

Therefore, in practice, there are operations in which the terminal device is turned on and off, particularly when the switch is repeatedly turned on and off quickly when it is turned on. In response to such irregular operations, the voltage at the reset terminal of the CP in the microprocessor rises before the voltage at the power supply terminal reaches the required voltage enough to restore the correct initial setting state. There is a possibility that the CPU enters the operating state without realizing it, and the subsequent operation of the CPU becomes disordered, resulting in a state similar to the hermit state.

To prevent such a situation from occurring, the user can turn off the power switch SW and then turn it on again.
Although it is possible to bring the CPU into a normal operating state, there is a risk that chattering may occur at the contacts of the power switch SW, so it is desirable to ensure that the CPU is reset when the power is turned on. This will be explained in detail below with reference to the drawings.

FIG. 1 is a diagram showing a conventionally known method of resetting a CPU.

In the figure, 1 is a CPU, 2 is a charging/discharging circuit, 3 is a power rectifier circuit, and SW is a power switch. When the SW is turned on, commercial alternating current (generally AC 100V) is transferred to the power rectifier circuit 3.
The DC voltage E, (for example, 5V) is transformed and rectified by
is converted into direct current and applied to the charge/discharge circuit. In the charge/discharge circuit 2, the capacitor C is charged through the resistor R, and the voltage at the RESET terminal of the capacitor C rises according to a time constant determined by R and C.
The rise is gradual. The CPU itself has its power supply terminal V
When the voltage E applied to cc reaches the operation guaranteed voltage level and the reset terminal voltage V Minami Arashi is maintained below the L level, a reset is performed to the initial state, and V Maeura becomes the H level voltage. After reaching VH, the CPU is in a normal operational state.

Further, when the switch SW is turned off, the electric charge of the capacitor C is discharged through the diode D in a short time, and Vcc and Vmin fall to OV, and the CPU becomes inactive. However, in the circuit shown in FIG. 1, if the SW is repeatedly turned on and off quickly or if the SW is chattering, there is a risk that the CPU will not be completely reset.
This will be explained with reference to FIG. In FIG. 2, the horizontal axis shows time and the vertical axis shows voltage. Vcc is the power supply voltage of the CPU, V is the reset terminal voltage of the CPU, V and L are the CP
U input L level voltage, VH is CPU operation guaranteed voltage,
T. indicates the time when the power switch is first turned on, t indicates the time when the power is turned off, and t indicates the time when the power is turned on again. Time T when Vcc becomes VH by turning on the power switch SW
At time T3, since V is still at V-L, the CPU is reset to the initial state, and at time T3, even before V is ready, it reaches VH, and the CPU returns to a normal operating state. However, time T4
If you disconnect the SW at and immediately turn on the SW at time T5,
Vcc; At time T6, which is the V day, the V level becomes V and L and is not cut off, so the reset is not applied. This is SW
By closing SW immediately after disconnection, charging starts again before the charge in capacitor C (2 in Fig. 1) is completely discharged by diode D, and as a result, Vcc becomes > VH at time T6.
This is due to the fact that the state of V arashiku < V, L does not occur in .

FIG. 3 shows an example of a circuit configuration for implementing the microprocessor CPU reset method according to the present invention, in which 1 indicates the CPU;
2 is a voltage monitoring control circuit, 3 is a power rectifier circuit, and SW is a power switch.

The power supply rectifier circuit 3 is configured to simultaneously and separately output a voltage E as a first rectified output (for example, a steady voltage of +5 V) and a higher voltage E2 (for example, a steady voltage of 112 V) as a second rectified output. be done. Terminal devices using a microprocessor, such as key telephone devices, multi-function telephones, data terminals, etc., may require the second rectified output E2 for signal amplification, lighting of a light emitting display, etc. Therefore, it is convenient to use this rectified output E2 for power supply monitoring as described below. As shown in the figure, the supervisory control circuit 2 includes a CR charging/discharging circuit having a Zener diode ZD as an input element, and a transistor TR whose front stage is grounded with its emitter. The charge voltage of the CR charging/discharging circuit is applied to the bases of the transistor TR. It consists of a two-stage transistor amplification line connected in this way.

As shown in the figure, this transistor amplifier circuit is connected so that the output voltage of the load R5 of the transistor TR2 in the subsequent stage is applied to the reset terminal RESET of the CPU.

Also, the first rectified output E, of the power supply rectifier circuit is V of the CPU.
cc terminal and transistor amplifier circuit TR and T
A second rectified output E2 is supplied as a power source for R2, and a second rectified output E2 is applied to a charging/discharging circuit consisting of R, , R2 and C via a Jenner diode ZD.

Here, the Jenner diode ZD plays the role of an input switching element, and becomes conductive when the potential difference between the voltage of E2 and the charge voltage of C exceeds the Jenner voltage value (for example, 7V), and when it becomes less than It becomes non-conductive. Figure 4 shows the power switch SW
C when turning on, cutting off, and turning on again in a short period of time
FIG. 3 is a diagram showing changes in the power supply terminal voltage Vcc and reset terminal voltage V of the PU. The operation of the implementation shown in FIG. 3 will be described below in comparison with FIG. 4.

When the power supply SW is turned on at time T, the power supply voltage Vcc applied to the CPU is the first rectified output E, and the power supply rectifier circuit generally increases the voltage with a time constant of ten seconds or more.

As shown in the figure, Vcc exceeds the guaranteed operation voltage VH of the CPU at time L, and then slightly exceeds this and reaches a steady voltage value (15 V) at E. However, "E, is applied to the base of TR2 through R3 and R4, so initially TR2
Since no current flows through the terminal, the RESET terminal remains almost at the sericulture level. On the other hand, the second rectified output E2 of the power rectifier circuit 3
is applied to the Zener diode D while increasing at a voltage higher than that of the first rectified output E with approximately the same time constant as that of the first rectified output E. The time point at which E2 exceeds the ZD voltage (for example, 7 V) is approximately the same as T2 or slightly later than T2. When E2 exceeds ZD's Jenner voltage Vz, ZD
becomes conductive, and the voltage at the connection point between the plate and R is (E2-
V2) The voltage begins to rise as E2 rises.

Along with this, charging begins in the capacitor charging/discharging circuit in which R is a series resistor and R2 is a parallel resistor. C=number rF, R,
If you choose =R2=several k0, the charging time constant is approximately 10ms.
That's about it. The charge voltage of capacitor C begins to rise slowly from the drop potential, and when it approaches IV, a current begins to flow between the base and emitter of TR.

Along with this, the amplified current flows between the collector and emitter, and the voltage drop across resistor R3 causes the collector potential of TR to drop, and due to the polarity reversal and amplification action in TR2, the reset terminal voltage V is approximately equal to It rises rapidly from the state of potential. This point in time is T3. After passing L, V branch is V
cc, it increases to a value almost close to the steady voltage E,. The period between time T2 and time T3 is a period in which Vcc exceeds VH and V raindrops are below V, L. During this period, the CPU automatically enters a reset state, and after T3, the CPU is in a normal operable state. Become.

According to the present invention, the stable and reliable set period, that is, T2
It is understood that the time between -T3 (several kite seconds or more) could be easily realized.

Next, consider a case where the user turns on the SW immediately after turning it off, either by mistake or with the intention of ensuring that the power is turned on. When SW is disconnected at time T4, Vcc drops as shown, but when SW is turned on again at time T4, Vcc increases in voltage again and exceeds VH to reach E. During this period, V Kagiritomi suddenly drops slightly after time T4 as shown by the dashed line in the diagram, but the reason for this is explained in the third section.
This will be explained below with reference to the figures.

As the SW is disconnected, the second rectified output E2 begins to drop.

E2 decreases in almost the same tendency as E, but when it falls below, for example, 8V [charge potential of Zener voltage 1C], the conduction of ZD is cut off. As a result, the charge on capacitor C becomes TR,
Since discharge begins between the base and emitter of and through R2, the voltage drops at a slightly faster rate than in the case of charging described above.

When the base voltage of TR falls below a certain potential, for example 0.7V, the current between the base and emitter starts to decrease rapidly, which causes the collector voltage of TR to suddenly increase, and therefore the current of TR2 to decrease rapidly, and V It suddenly drops to near zero potential. Reliability cannot be expected unless the reset operation is performed before Vcc falls below the guaranteed voltage VH.

According to an embodiment of the present invention, it is possible to drop the V-level rapidly within 3 ms from the time when the Zener diode becomes non-conductive.

Note that since the Zener diode must begin to become non-conductive before Vcc drops below VH, a method is used to detect the drop in the second rectified output E2, which is higher than E, more quickly than the Zener diode. .

As a supplementary explanation, E and E2 output from the same rectified power supply system generally rise and fall with approximately the same time constant, so the absolute value of the voltage drop of the higher rectified output is that of the lower one. It takes advantage of the fact that the voltage drop of the rectified output is larger than that of the rectified output. Therefore, in the present invention,
It is essential to provide a power supply rectifier circuit that separately generates a first rectified output to be supplied to Vcc of the microprocessor CPU and a second rectified output higher than the first rectified output.

Once VR838T becomes below V,L and the CPU is reset, E, will rise again at time T5 by turning on the SW again, but in this case, from the time T, when the SW is turned on for the first time, to the time The various circuits in the supervisory control circuit operate in the same way as in the process leading to time T3 via L. As explained above, according to the present invention, even if chattering occurs in the contacts of the power switch due to the operation method when the user turns on the power switch, or when the user turns on and off the power switch repeatedly, However, it has the advantage of ensuring a reliable reset, and can be applied to a wide range of applications such as data communication and telephone terminal devices, and its effects are extremely large.

[Brief explanation of the drawing]

Figure 1 shows an example of a known circuit configuration for resetting the CPU of a microprocessor. 1 is the CPU, 2 is a charging/discharging circuit, 3 is a power rectifier circuit, and SW is a power switch. Figure 2 is the circuit configuration example shown in Figure 1. FIG. 6 is a diagram showing changes in the power supply terminal voltage and reset terminal voltage of the CPU when the SW is turned on, cut off, and turned on again within a short period of time. FIG. 3 is a block diagram showing an embodiment of a microprocessor CPU reset method according to the present invention, in which 1 is a CPU, 2 is a voltage monitoring control circuit, 3 is a power rectifier circuit, and SW is a power switch. Figure 4 shows the CPU when the power switch SW is turned on, turned off, and turned on again in a short time in the configuration diagram of Figure 3.
FIG. 3 is a diagram showing changes in the power supply terminal voltage and reset terminal voltage of FIG. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 In a terminal device that uses a microprocessor,
It is equipped with a power rectifier circuit that simultaneously and separately generates a first rectified output and a second rectified output of a higher voltage, and a CR charging/discharging circuit using a Zener diode as an input switching element, and a transistor whose emitter is grounded at the front stage. A supervisory control circuit is provided which includes a two-stage amplification transistor amplifier circuit connected so that the charge voltage of the CR charging/discharging circuit is applied to the base of the microprocessor, and the first rectified output is connected to the microprocessor CPU terminal and the The second rectified output is supplied to the charge/discharge circuit via a Zener diode, and the output of the latter stage of the transistor amplifier circuit is supplied to the reset terminal of the CPU. A reset method for a microprocessor CPU, characterized in that the reset terminal voltage is maintained at an L level or lower for a longer period of time when the power is turned on by connecting the reset terminal to the reset terminal.