JPS6045461B2 - Analog signal calculation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device using a processor such as a microcomputer.

With recent advances in digital circuit technology, microcomputers and other processors have become smaller and more affordable, and as a result, attempts have been made to incorporate microcomputers into analog processing devices. ing.

In this case, an analog-to-digital converter 1 for converting an analog signal into a digital signal is installed on the input side of the processor 2 as shown in FIG. It is necessary to provide a digital-to-analog converter 3 respectively. However, both A/D converters and D/A converters have complex circuit configurations and are expensive, so even if only the processor 2 becomes cheaper, it will not lead to a reduction in the price of the entire device. . Here, the present invention provides an A/
Does not require a D converter or a D/A converter on the output side. Therefore, the present invention aims to realize a device of this type that has a simple overall configuration and is inexpensive. FIG. 2 is a block diagram showing an embodiment of the present invention.

In the figure, 11 is an input terminal to which an input analog signal e1 is applied, 20 is a comparator that receives the input analog signal e1 as one input, and 2 is a processor that receives the signal from the comparator 20. For example, a microcomputer used. E, generally indicates the reference voltage source, Sl, S2
are switches, both of which are driven by a pulse width signal from the processor 2. Note that if the reference voltage sources E, and switches Sl and S2 are obtained by internal functions of the processor 2, they can be omitted. 31,
32 is means for converting a pulse width signal into an analog signal;
Here, both resistors Rl and R2 and capacitors Cl and C
This uses a filter circuit composed of 2 and 2.

The input end of the filter circuit 31 is connected to the reference voltage source Es via the switch S1, and the output end is connected to the other input end of the comparator 20. Further, the input end of the filter circuit 32 is connected to the reference voltage source E via the switch S2, and the output end is connected to the output terminal 41. The operation of the apparatus configured as described above will be explained below, dividing into the case where the input analog signal E is converted into a digital signal and the case where the calculated result is converted into an analog signal. [Analog-digital conversion operation] In this operating state, the processor 2 uses the comparator 20,
A loop including a switch S1 and a filter circuit 31. A pulse width signal converter for converting the input analog signal E, into a corresponding pulse width signal is constructed using a pulse width signal converter, as shown in FIG. A pulse width signal with a duty ratio t/T as shown in FIG.
Output to.

: When the switch S1 is turned on and off by this pulse width signal, the reference voltage Es supplied to the filter circuit 31 is turned on and off at t/T, and from the output terminal of the filter circuit 31 is expressed by equation (1). A voltage E, such as this is obtained, and this value becomes equal to the input analog signal E, if the gain of the comparator 20 is sufficiently large. Therefore, the reference power source E
If the Sl period T is constant, the pulse width t of the pulse width signal output from the processor 2 corresponds to the input analog signal Ei, and a digital signal corresponding to e1 is obtained in the register means in the processor 2.

In the A/D conversion operation described above, the operation of generating a pulse width signal by the processor 2 is performed while observing the output signal of the comparator 20 according to a program provided to, for example, a program memory of the processor 2. It will be done.

FIG. 4 is an example of a block diagram equivalent to the pulse width signal generation operation of the processor 2 using hard logic in order to make it easier to understand.

In this block diagram, the output signal of the comparator 20 is applied to gate circuits 7G1 and G2. For example, if the output signal is ゜"1゜, the gate circuit G1 is opened, and if it is "゜0゜, the gate circuit G2 is opened. . As a result, the up/down counter COU counts up the clock pulse CP if the output signal of the comparator 20 is ゜゜1゛,
If so, count down. Therefore, the up/down counter COU finally has a count value RE1 corresponding to the input analog signal E. counter CO
T counts clock pulses CP, and its count value R
Ao becomes a signal like A in FIG. 5A, which repeats gradually increasing up to the maximum count value of this counter. The digital comparator COM compares the count value EI of the up-down counter COU with the count value A of the counter COT, and as shown in the opening of FIG.
During the period T-t when A≧EI, “゜0゛” is output. Therefore, the output terminal TO of the digital comparator COM
From this, a pulse width signal with a duty ratio determined by the input analog signal and the maximum count value of the counter COT can be obtained. Further, a digital signal corresponding to the input analog signal E is obtained from the up/down counter COU.
The processor 2 implements the A/D conversion operation described above using, for example, software.

r The digital signal thus obtained is used within the processor 2 to perform desired calculations. [Digital-analog conversion operation] In this operating state, the processor 2 outputs the calculation result in the form of a pulse width signal to the switch S2.

When the switch S2 is turned on and off by a pulse width signal corresponding to a digital signal, the reference voltage Es supplied to the filter circuit 32 is turned on and off, and the filter circuit 3
An analog voltage EO corresponding to the digital signal can be obtained at the output terminal 41 of No. 2. Note that, within the processor 2, the operation of outputting the digital calculation result to the switch S2 as a pulse width signal is realized by, for example, software.

The device according to the present invention has an A/D on the input/output side of the processor 2.
Since no converter or D/A converter is required, the overall configuration is simple and inexpensive.

Furthermore, since the connection with the processor 2 only requires a single input/output signal to occupy several I/0 ports, the limited number of I/0 ports can be effectively used in the processor 2. . FIGS. 6 to 8 are block diagrams showing other embodiments of the present invention.

In the embodiment shown in FIG. 6, one filter circuit is provided on the output side of the processor 2 and is used in a time-sharing manner, and the output terminal of the filter circuit 30 is connected to the other input terminal of the comparator 20. It is also connected to the input end of the sample and hold circuit .beta.H.

Furthermore, a pulse width signal from the processor 2 is applied to the input end of the filter circuit. Note that the sample hold circuit SH here includes a sample switch S1 driven by a signal from the processor 2, a capacitor C, and an amplifier A. According to this embodiment, the processor 2 performs A/D conversion using a loop including the filter circuit 30 and the comparator 20 (in this state, the switch S
is off), a filter circuit, and a sample-and-hold circuit SH perform D/A conversion (in this state, the processor 2 does not read the output of the comparator).

In the embodiment of FIG. 7, the output signal of the comparator 20 is applied to the processor 2 via the isolator means 1S1,
The pulse width signal from the processor 2 is transmitted to the isolator means 1.
It is coupled to filter circuits 31 and 32 via S2 and IS3, respectively.

Note that although the isolator means used here are both a photodiode and a phototransistor, means such as a transformer may also be used. In the device according to the invention, the signal applied from the comparator 20 to the processor 2 is “
It is a binary signal of ゜1゛ or 0゛, and the signal output from the processor 2 to the filter circuit is also ゜“1” or
Since it is a pulse width signal composed of a binary signal of 0゛,
As shown in this embodiment, there is a practical effect that signals can be easily isolated between input and output.

The embodiment of FIG. 8 uses an integrator 1NT as a filter circuit 30, a circuit SH2 that samples and holds the output of this integrator, and an output of this sample and hold circuit SH2 that is connected to the input side of the integrator INT. This uses a section averaging circuit consisting of a feedback circuit R, which feeds back to .

By using the interval averaging circuit having such a configuration, an analog signal corresponding to the pulse width signal can be obtained from the output end of the filter circuit 30 in a shorter time than that of the embodiment of FIG. In each of the above embodiments, the case where one analog signal is input and one analog signal is output is shown, but the present invention can be similarly applied to the case where a plurality of analog signals are input/output.

As described above, according to the present invention, it is possible to realize an analog signal processing device that has a simple overall configuration and can effectively utilize the limited number of I/O ports of a processor.

Furthermore, it is possible to realize this type of device in which signal isolation can be easily performed if necessary.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an analog arithmetic unit using a conventional processor, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of the output from the processor in FIG. A waveform diagram showing the waveform of a pulse width signal, FIG. 4 is a block diagram equivalent to the pulse width signal generation operation of the processor 2 in FIG. 2 using hard logic, and FIG. 5 is an explanation of the operation of the block diagram in FIG. 4. 6 to 8 are block diagrams showing other embodiments of the present invention O. 20... Comparator, 2... Processor, 31, 32.
...filter circuit, SH...sample hold circuit,
ISl to IS3: isolator means.

Claims (1)

[Claims] 1. A comparator that receives an input analog signal as one input, a processor that receives the signal from this comparator as input, and obtains an analog signal corresponding to a pulse width signal output from this processor and processes the analog signal. filter means for applying a signal to the other input of the comparator, the processor obtaining a digital signal corresponding to the input analog signal by configuring a loop including the filter means and the comparator; An analog signal calculation device in which a result calculated by a processor is obtained as an analog signal via the filter means or another filter means. 2. A switch is provided that is driven by a pulse width signal output from the processor, and a reference voltage on/off signal obtained through this switch is applied to the input side of the filter means and corresponds to the pulse width signal from the output side. 2. The analog signal calculation device according to claim 1, wherein the analog signal is obtained by obtaining a calculated analog signal. 3. The analog signal calculation device according to claim 1, wherein the result calculated by the processor is obtained through a filter means and a sample and hold circuit. 4. The analog signal processing device according to claim 1, wherein isolator means is inserted on the output side of the comparator and on the input side of the filter means. 5. A section averaging circuit comprising an integrator, a circuit that samples and holds the output of the integrator, and a feedback circuit that feeds back the output of the sample and hold circuit to the input side of the integrator as the filter means. The analog signal calculation device according to scope 1.