JPS6045482B2 - Optimal recording equalizer characteristic detection method for magnetic recording and playback equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting optimum recording equalizer characteristics for a magnetic recording/reproducing machine, and more particularly to an optimum recording equalizer characteristic detection method for automatically detecting optimum recording equalizer characteristics for a two-head tape recorder.

There are different types of magnetic tape, such as L-H tape, chrome tape, and ferrichrome tape, and tape recorders are usually adjusted using the standard tape for each type, but even tapes of the same type have different characteristics. Largely, these various positions, Ih-A-j-■l■-dA-
[PLJ-, L-, ii] Ita 11--几Pi 1↓fu, is becoming difficult.

An object of the present invention is to automatically detect recording characteristics for various tapes, particularly optimal characteristics of recording equalizer characteristics.
An object of the present invention is to provide a method for detecting optimal recording equalizer characteristics in a head type tape recorder.

The optimal recording equalizer characteristic detection method of the present invention sets the recording bias current and the recording signal level to predetermined values, and records while sequentially varying the recording compensation amount for the recording signal between the upper limit and the lower limit in multiple steps. Then, while sequentially reproducing the recording compensation amount variable steps from the beginning, the reproduction level of the recording signal at each step is stored in the storage means, and each of the reproduction levels stored in the storage means and the predetermined reference level are respectively The present invention is characterized in that a recording compensation amount corresponding to a playback level equal to a predetermined reference level is set as the optimum value by comparison.

The present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a lock diagram of a circuit for an embodiment of the present invention, and shows a mid-low frequency signal f for recording bias and recording level adjustment.

(333H2) and a high frequency signal fH (10Kl12-) for adjusting a recording equalizer (EQ) are selectively selected by the changeover switch 1 and input to the line switch 2. The line switch 2 selects either the line input signal or the aforementioned adjustment signal (f or FH) and applies it to the flat amplifier 3. The amplified signal is input to the recording level setting circuit 4, and its level is varied and set to an appropriate level. Thereafter, the signal is applied to the recording equalizer setting circuit 5. This circuit 5 has a configuration in which the equalizer characteristics are variable, and its output is the recording bias signal F8
(100KHz) and the recording/playback switch 10
The data is recorded onto the tape 7 by the R/P head 6 via the R/P head 6.

The recording bias FB is applied to a recording bias setting circuit 8 for varying and appropriately setting the bias current value, and its output is superimposed on the recording signal.

The tape recording signal is reproduced by the R/P head 6, amplified by the reproduction amplifier 11 via the switch 10, and then input to the detection circuit 15.

In this detection circuit, the reproduced signal is converted to a DC level and becomes one input of the comparator 16. The reference signal which is input from this comparator 16 is the D/A converter 17.
This converter converts the parallel binary digital signal output from the port output PA of the microprocessor 18 to a DC level.
The output of comparator 16 is applied to the boat input P1 of microprocessor 18. Binary digital signals are output from the boat outputs PT3, PC, and PO of the processor 18, respectively, and these signals are used as control signals 101 and 102 for controlling the recording level setting circuit 4, the EQ setting circuit 5, and the bias setting circuit 8. and 103.

The changeover switch 1, line switch 2 and R/P switch 10 are the boat outputs P2 and P3 of the processor 18, respectively.
The on/off control is performed by P4 and P4, and the boat output P5
is used as a control signal to control the mechanical system of the tape recorder, and a control signal from the mechanical system is similarly input to the boat input P6.

A memory 19 including a ROM in which a program for controlling the microprocessor 18 is stored in advance and a readable/writable RAM is provided, and a keyboard 20 is connected to provide external commands. The keyboard 20 may be provided with a display so that the control status of the microprocessor can be monitored. In addition, the RAM of memory 19
During normal operation, power is supplied from the device power supply, but when the power is turned off, power is supplied from a so-called backup power source such as a battery, so that the memory contents can always be retained. It is becoming. FIG. 2A shows a specific example of the recording level setting circuit 4, in which the impedance between the input/output line and the ground is varied by a parallel 6-bit digital control signal 101 from the microprocessor 18. For this purpose, the switching transistor Q1 resistor network R, 2R,..., 3
It is composed of 2R and D-7FF.

The input/output ratio of the recording level corresponding to the control signal 101 is shown in FIG. The magnitude of the 6-bit control signal 101 is digitally expressed in 64 steps from the minimum value 00 (H) to the maximum value 3F' (in hexadecimal notation).
In (H), the control signal 101 is (000000), indicating step 0, and the control signal 101 is (111111), indicating step 6.
3, and 20 (H) is the intermediate step (1000
00).

Here, the recording level is changed stepwise in 64 steps using a 6-bit control signal, but increasing the number of bits will widen the variable range and increase the resolution. Note that (H) indicates that the signal is expressed in hexadecimal notation, and the same applies to the other control signals 102 and 103.
FIG. 3A shows a specific circuit example of the recording bias setting circuit 8, in which the resistance value between the bias signal line and the ground is varied according to the 6-bit control signal 103 of the processor 18, and the resistance value of the switching transistor Q1 resistance network R ,2R,...
, 32R. ．． It consists of a D-FF, an inverter IN, etc. 801 indicates a bias amplifier that amplifies 100 KHz.

FIG. 5B shows how the bias signal current changes with respect to the control signal 103. FIG. 4A shows a specific example of the recording equalizer setting circuit 5, in which the control signal 10 of the processor 18 is
2, the value of the capacitive element Cs for equalizer characteristics is changed to appropriately select the amount of compensation for the 10 KHz signal, and the operational amplifier 0P1 switching transistor Q1 capacitor network C, 2C, 32C, D-FF, etc. Consists of.

B in the same figure shows the change in capacitance value with respect to the digital control signal 102, and C shows the frequency characteristic of the recording signal current using the digital control signal 102, that is, the capacitance value as a parameter. The operation of the present invention will be explained below using FIGS. 5 to 7. First, press the "START" button on the keyboard 20 (
(not shown), a start signal for automatic adjustment is input from the keyboard to the micropressor 18.

In response to this start signal 4, the operation is started according to the procedure indicated in the program stored in the ROM in the memory 19. First, the boat output P3 of the processor 18
The switch 2 is controlled to prohibit line input, and the boat output P5 causes the mechanical system to enter the recording state.

At this time, the switch 10 is also switched to the recording state by the boat output P4, and the selection switch 1 is controlled by the boat output P2 to select the signal FL. And RA in advance
The data stored in M is the boat output PB, PC
and Pc. The recording level setting circuit EQ setting circuit 5 and the bias setting circuit 8 are set and controlled to their standard states. In this state, as shown in Figure 5,
Time T.

The mid-low frequency signal FL is recorded at a standard level between times t1 and t1, and no signal is recorded between times t1 and T2. During this period, the bias is at the standard value as shown by the dotted line. This period is used to record a so-called marker signal for detecting the starting point position for the next reproduction stage. It’s time~
During T3, the signal FL is again fixed at the standard level, and the bias current is varied from the minimum to the maximum as shown by the dotted line in the figure, that is, the control signal 103 is varied from 00 (H) to 3.
Recording is continued by sequentially changing in 64 steps up to F' (H).

Thereafter, the tape is stopped at a certain time, and the tape is rewound to the part where the start signal is recorded (corresponding to TO) and brought to a stopped state. This stop position can be stored in the internal memory of the microprocessor 18 or in the external memory 19. Next, the mechanical system is controlled to the reproducing state, and the R/P switch 10 is switched to the reproducing side.

In this case, for example, the minimum value 00 (H) of the digital signal is output from the boat output PA, and the minimum DC level is applied by the D/A converter 17 as a reference input to the comparator 10. Therefore, at time T4, the comparator output is inverted and the rise of the reproduced signal FL is confirmed, and the period T4 to T6 is completed.
It will be in standby mode for a while. At this time, the fall of the reproduced signal FL may be confirmed by the output of the comparator, and the period T6 may be set as a standby state. At time t, the reproduction level of the signal FL is A/D converted into a digital signal by a so-called sequential comparison type A/D converter including a comparator 16 and a D/A converter 17. Therefore, the reproduction level for each step during period T6 is converted into a digital signal and stored in each predetermined location in the RAM.
Thereafter, the digital signals corresponding to the respective stored playback levels are processed in the microprocessor 18, and the digital signal corresponding to the maximum level is detected.

The recording bias current value corresponding to this level is the optimum recording bias. The recording bias current value at this time can be easily determined, for example, by associating each storage address of each digital signal with the variable step number during recording. At this time, the tape is rewound again to the starting position in preparation for the next adjustment step.

The recording bias current value thus set can be stored in the RAM by pressing a predetermined switch on the keyboard 20, and can be read out by a similar operation. Next, the recording level is adjusted as shown in FIG. That is, the low/mid range signal FL is selected and set to the standard level, and the EQ setting circuit 5 and bias setting circuit 8 are also set and controlled to be in the standard state.
Then, time T in FIG. - The same operation as T2 is performed, and then the bias setting circuit 8 is set and controlled by the control signal 103 so that the optimum recording bias current detected earlier is set, and the signal FL is controlled from time T2 to T3. The control signal 101 controls the recording level from the minimum to the maximum.
are sequentially varied and recorded in 64 steps. Thereafter, from time T3 to time T7, the same operation as that shown in FIG. 5 is performed. After all re-output signal levels FL are digitally stored at a certain time, a predetermined reference level E previously stored in the memory and these digital reproduction signals are compared in the microprocessor, and the reference level E and Equal digital signals are detected. The recording level corresponding to the digital signal at that time is the optimum value, and the recording level at this time can also be set by making each storage address of each digital signal correspond to the variable number of steps during recording. At this time, the tape is rewound to the starting position again. The recording level thus set can be stored in the RAM and read out.

Finally, the EQ characteristics are adjusted as shown in FIG.

That is, the high frequency signal FH is selected and set to the standard level, and the EQ setting circuit 5 and bias setting circuit 8 are also controlled to be in the standard state. And time T in FIG. −
Exactly the same operation is performed, and then the bias setting circuit 8 and the recording level setting circuit 4 are controlled and set using the control signals 103 and 101 so as to have the optimum values detected earlier, and from time T2 to T3. control signal 102 between
Recording is performed by changing the amount of recording compensation for the high frequency signal FH by changing it in four steps. Then time T3-T
7, the same operation as that in FIG. 5 is performed. After all reproduced signal levels f) are digitally stored at time intervals, these digital signals are compared with the reference level E previously stored in the memory in the microprocessor, and the reference level A digital signal equal to level E is detected.

The recording compensation amount corresponding to the digital signal at that time indicates the optimum value, and the optimum recording EQ characteristic can be obtained. Finally, the tape returns to the starting position and stops, the line input inhibition is canceled, and the normal state is restored.

In the above embodiment, the recording bias, level, etc. are varied in ascending order from the minimum step to the maximum step, but the order of variation is not limited to this, and can be changed as appropriate between the minimum and maximum steps. Just make it variable.

As described above, according to the present invention, the memory, microprocessor, etc. can be configured with a microcomputer, and an extremely small and highly reliable device can be obtained.

Another advantage is that optimum recording characteristics can be automatically determined for any type of tape.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram for an embodiment of the invention, FIG.
Figure A shows an example of a recording level setting circuit, B shows its characteristics, Figure 3 A shows an example of a recording bias setting circuit, B shows its characteristics, and Figure 4 A shows an EQ setting circuit. B and C are its characteristic diagrams, Figure 5 is an explanatory diagram of the operation for adjusting the recording bias, Figure 6 is an explanatory diagram of the operation for adjusting the recording level, and Figure 7 is an illustration of the EQ adjustment. This is a special explanatory diagram for. Explanation of symbols of main parts, 1...Recording level setting circuit, 5...EQ setting circuit, 8...Recording bias setting circuit, 18...Microprep Sessa, 19...Memory.

Claims (1)

[Claims] 1 Set the recording bias current and the recording signal level to predetermined values, record while sequentially varying the recording compensation amount for the recording signal between the upper limit and the lower limit in multiple steps, and then set the recording compensation amount to the first value. While sequentially reproducing from the step, the reproduction level of the recording signal in each of the steps is stored in a storage means, and each of the reproduction levels stored in the storage means is compared with a predetermined reference level set in advance. A method for detecting an optimum recording equalizer characteristic for a magnetic recording/playback device, characterized in that the recording compensation amount corresponding to a playback level equal to the predetermined reference level is set as the optimum value.