JPS6045828B2 - mask memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mask memory that enables more effective and efficient failure analysis of semiconductor circuits.

Figure 1 shows the configuration of a conventional mask memory.
1 is a test pattern generator, 2 is a circuit under test, 3 is a comparator, and 4 is a mask memory.

FIG. 2 shows an example of a test process when a memory circuit is assumed as the circuit under test 2. In FIG. To explain the operation of the mask memory 4 using FIG. 1, first, a so-called test pattern such as an address signal, a data signal, a read command signal, a write command signal, etc. is applied to the circuit under test 2 from the test pattern generator 1. . The circuit under test 2 receives the test pattern and outputs predetermined write information during a predetermined operation, such as a read operation. The mask memory 4 receives a read command signal (READ) generated by the test pattern generator 1.
Alternatively, the cycle clock (CLK) is used as the operating clock, and the address information applied to the circuit under test 2 or the output of a counter that counts the cycle clock is received as its own address information, and some method is used in advance before starting the test. The information stored in the comparator 3 regarding execution or prohibition of the comparison operation is read out and sent to the comparator 3 as a comparator control signal. The comparator 3 uses the expected value pattern generated by the test pattern generator 1 and the circuit under test 2.
When the comparator control signal mentioned above is not a comparison prohibition command, the output information output from
If there is a mismatch, it is determined as "Fair". Also, when the comparator control signal commands a comparison prohibition, the comparator output is always in the "Pass" state regardless of the input state.Specifically, first, test execution is performed. Before the comparison prohibition information is written to the address position of the mask memory 4 corresponding to the address position where comparison is prohibited in the circuit under test 2. During the test execution, the test target part of the circuit under test 2 is tested and the read command is During execution, the comparison prohibition information of the address position corresponding to the test target address of the circuit under test 2 in the mask memory 4 is simultaneously read out and sent to the comparator 3 as a comparator control signal.
When the comparator 3 executes this read command and the comparator control signal is a comparison prohibition command, the comparison result between the output information of the circuit under test 2 and the expected value pattern from the test pattern generator 1 is ゜゜Pass゛. Only when the comparison control signal is not a comparison prohibition command, the output information of the circuit under test 2 is compared with the expected value pattern, and if they match, it is judged as ゜゜Pass, and when they do not match, it is judged as "Fair". As a result, it is possible to test a specific area in the circuit under test 2 without prohibiting comparison without being affected by other areas.The above is a conventional mask memory test. In such a conventional mask memory, within the same test pattern sequence as shown in Fig. 2, some parts test the entire area of the circuit under test, while other parts test only a specific area. It is difficult to conduct an irregular test method such as performing a detailed test without being shifted, and there is no choice but to use or not use the mask memory in common within the same test pattern sequence, as shown in Figure 2. The drawback was that it was not possible to implement a test method such as the one shown in Fig. In this method, there was a big problem that the test results did not necessarily match the original test, that is, the test shown in Figure 2.The present invention aims to solve this problem by changing the test pattern sequence. This makes it possible to enable the comparison prohibition function for the mask memory comparator in an arbitrary area.The drawings will be explained in detail below.Figure 3 shows one embodiment of the present invention. The difference from the diagram is that the mask memory 4 includes a start counter 41, a stop counter 4, and gate circuits 42, 4.
5, 50, multiplexers (MPX) 43, 46, a start counter enable register 47, a stop counter enable register 48, and a conversion circuit 49. The comparator control signal, which is the output information of the memory section 40, is sent to the comparator 3. A control section is provided to control the input of , and this control section enables the comparison prohibition function for the comparator 3 of the mask memory 4 to be enabled only in an arbitrary area within the test pattern sequence.

Since the operation of the memory section 40 itself is basically the same as in the past, the operation will be explained below with a focus on its control section. Now, the start counter 41 is set to an arbitrary value in advance before the test is executed, and its contents are decremented for each read command or cycle clock of the test pattern sequence. The comparator control signal is made effective for the comparator 3 from the time when the value becomes equal to the initial setting value.

The start counter enable register 47 is a 1-bit register that instructs whether to enable or disable the control function for the comparator control signal of the start counter 41. The start counter enable register 47 is a 1-bit register that instructs whether to enable or disable the control function for the comparator control signal of the start counter 41. A value of 1゛ is set.The multiplexer 43 receives the state of the start counter enable register 47 (start counter enable flag 51), and if it is ゜゜0゛, it generates a test pattern to enable the comparator control signal. Select READ/CLK of the device 1, and if it is “゜1゛”, the gate circuit 4 under the control of the start counter 41
Select output 2.

Like the start counter 41, the stop counter 44 is set to an arbitrary value in advance before the test is executed, and when the start counter 41 is invalid, after the start of the test, the contents are read out at each test pattern sequence read command or every cycle clock. , and the comparator control signal is enabled until the content becomes zero, that is, the number of read commands becomes equal to the initial setting value of the counter 44, or when the start counter 41 is enabled, the content of the start counter 41 becomes zero. From the point at which the test pattern sequence is read out, its contents are decreased every time the test pattern sequence is read out or every cycle clock, and the comparator control signal is enabled until the contents become zero.Stop counter enable register 4
8 is a 1-bit register that instructs whether to enable or disable the control function for the comparator control signal of the stop counter 44, and like the register 47, it is set to "0" or "1" in advance before the test is executed. Set the value of ゛. The multiplexer 46 receives the state of the stop counter enable register 48 (stop counter enable flag 52), and if it is ゜“0゛, it selects the output of the previous stage multiplexer 43, and if it is ゜゜1゛, it selects the output of the stop counter 44. gate circuit 45
Select the output of Figure 4 summarizes the relationship between the setting states of the start counter 41, start counter enable register 47, stop counter 44, and stop counter enable register 48 and the special mode of the mask memory, and the solid line indicates the valid period of the comparison prohibition information. (during mask operation), and the broken line indicates an invalid period (during mask suspension).

Specifically, for example, the start counter 41 is set to 10, the stop counter 44 is set to 20, and the start counter enable register 47 and stop counter enable register 48 are each set to "゜1゛" (in Fig. 4, The start counter enable flag indicates the setting state of the register 47, and the stop counter enable flag indicates the setting state of the register 48). The comparator 3 is enabled because the comparator control signal from the 1st cap is disabled, and the stop counter 44 operates from the 1st cap until it counts the 2nd read command. Since the comparator control signal is inhibited again from then on, the comparator 3 is enabled, and the test shown in Figure 2 becomes possible.The conversion circuit in Figure 3 By reversing the output of 49, the comparison prohibition information valid period and the comparison prohibition information invalid period shown in FIG. 4 are reversed, making it possible to perform more irregular tests.

As explained above, the mask memory according to the present invention enables the comparison prohibition function for the comparator of the mask memory (memory section) to be enabled in any area during the test pattern sequence. This method has the advantage that it becomes possible to perform an irregular test method, such as an interference test between memory cells of a memory circuit, in which comparator comparison is inhibited and inhibited.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional mask memory, FIG. 2 is a diagram showing an example of a test pattern sequence when the circuit under test is assumed to be a memory circuit, and FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a diagram for explaining the operation of FIG. 3.

Claims (1)

[Claims] 1. In the mask memory that controls execution or prohibition of the comparison operation of the comparator that compares the expected value pattern generated by the test pattern generator and the information output from the circuit under test at each step of the test execution sequence, a memory section in which information on a command to execute or prohibit a comparison operation of the comparator is stored in advance before execution, and outputs information on a position specified by an address signal from the test pattern generator as a comparator control signal; Setting an arbitrary value, updating the contents at each step of the test execution sequence, and starting to make the comparator control signal valid for the comparator from the time the contents reach a predetermined value. A counter is set to an arbitrary value in advance, and when the start counter is invalid, its contents are updated at each step after the start of the test execution sequence, and
When the start counter is valid, its contents are updated at each step of the test execution sequence from the time when the start counter reaches a predetermined value, and when the contents reach the predetermined value, the comparator control is performed. The method is characterized by comprising a stop counter that disables the signal, and means for instructing whether to enable or disable the control operation of the start counter and the stop counter with respect to the comparator control signal of the memory section. mask memory.