JPS604596B2 - Method of manufacturing complementary MOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a complementary MOS integrated circuit, and particularly to a method for manufacturing a complementary MOS integrated circuit.
The present invention relates to a method of manufacturing an OS integrated circuit.

Figures 1 to 3 show complementary MOSs manufactured using conventional manufacturing methods.
The manufacturing process of integrated circuits is briefly shown.

FIG. 1 shows that after an oxide film 2 is formed on an N-type silicon substrate 1, a hole is made in a part of the oxide film 2 by a method such as ordinary etching, and then a P-type impurity such as boron is diffused by a method such as a diffusion method. , which shows a state in which a P-type island region 3 is formed. FIG. 2 shows a state in which the oxide film 2 of FIG. 1 has been completely removed and then a field oxide film 4 is newly formed by a thermal oxidation method or the like. FIG. 3 shows the source region 5, drain region 6, and gate insulating film 7 of a P-channel MOS transistor and the source region 8, drain region 9, and gate of an N-channel MOS transistor formed on the wafer in the state shown in FIG. A state in which an insulating film 10 is formed is shown. For convenience of explanation, two N-channel MOS transistors are shown. In an actual complementary MOS integrated circuit, for example, there are many N-channel MOs in an island area.
There are S transistors and it is necessary to provide electrical isolation between these MOS transistors. In Figure 3, P
Electrical isolation between the two N-channel MOS transistors within the shaped island region is important. This is two N
A parasitic MOS formed between channel MOS transistors and using part 4' of the field oxide film 4 as a gate insulating film.
It is defined by the threshold voltage VTHF of the transistor. If this threshold voltage VTHF is not higher than the maximum operating voltage, leakage may occur between the N-channel MOS transistors during operation. However, in order to increase the value voltage VTHF, for example, {1} make the field oxide film 4' thicker, '2-reduce the interfacial charge Qss of the field oxide film 4', (3) make the field oxide film 4' There are methods such as increasing the substrate impurity concentration. (1) and {
Method 2' is also effective for the value voltage VMF if the substrate impurity concentration is high to some extent, but there is a limit when the substrate impurity concentration is low. Therefore, the value voltage V
To ensure that the T cape is high, especially for the N channel,
It is preferable to perform isolation diffusion directly under the field oxide film 4' to increase the impurity concentration near the surface of the P-type island region 3. However, if separation and diffusion is performed, the number of steps increases and the withstand voltage between the drain and the substrate decreases, so there is a limit. On the other hand, for a complementary MOS integrated circuit operating at a low voltage, it is required to lower the threshold voltage VTHN of both N-channel MOS transistors, and therefore the surface impurity concentration of the P-type island region 3 must be made as low as possible. No.

This requirement is contrary to the requirement that the threshold voltage VTHF be increased. Furthermore, when the field oxide film 4 is formed after the P-type island region 3 is formed, impurities near the surface of the P-type island region are sucked out into the field oxide film 4, and impurities directly under the field oxide film 4' are absorbed. The concentration further decreases, and therefore the value voltage VTHF decreases.If the isolation diffusion described above is not performed, the interfacial charge Qs of the field oxide film 4'
Depending on the value of s, the threshold voltage VTHF may be lower than the threshold voltage VTHN of the MOS transistor that must actually operate. Gate insulating film 10
The impurity concentration directly under the field oxide film 4' should not be lower than the impurity concentration directly below, and the interfacial charge Q
If ss can also be reduced appropriately, the threshold voltage VTHF can be increased by increasing the thickness of the field oxide film 4'.
It can be made higher than the value voltage VTHN. In the present invention, after forming a field oxide film having a plurality of holes spaced apart from each other on one principal surface of a substrate, forming an island region in the substrate through each of the holes, and forming an island region surrounded by the field oxide film. By forming MOS transistors so that the entire island region serves as an active region, the threshold and value of a parasitic MOS transistor using the field oxide film between each MOS transistor as a gate insulating film can be improved without performing isolation diffusion. The present invention provides a method for manufacturing a complementary MOS integrated circuit that can increase the voltage. 4 to 6 briefly illustrate the manufacturing process of a complementary MOS integrated circuit according to the manufacturing method of the present invention.

FIG. 4 shows a state in which a sufficiently thick field oxide film 4 is formed over the entire surface of the N-type silicon substrate 1. As shown in FIG. FIG. 5 shows that holes are formed in the field oxide film 4 in the active region of an N-channel MOS transistor, that is, the portions forming the source region, drain region, and channel region between these, by a method such as ordinary etching, and then by a diffusion method, etc. This shows a state in which a P-type impurity such as boron is diffused, thereby forming a P-type island region 3. FIG. 6 shows that a source region 5, a drain region 6, and a gate insulating film 7 of a P-channel MOS transistor are formed on a wafer in the state shown in FIG. 5 using a conventional method.
and the source region 8 of the N-channel MOS transistor.
, which shows a state in which a drain region 9 and a gate insulating film 10 are formed. What is particularly important here is that each N-channel MOS is
A transistor is formed. In this case as well, the third
As in the case shown in the figure, for example, the threshold value voltage V...F of the field oxide film 4' between two N-channel MOS transistors becomes a problem. Since the P-type island region 3 was formed by diffusing impurities such as boron after forming the very thick field oxide film 4, the surface impurity concentration in this part was reduced by the impurity concentration during thermal oxidation as in the case of Fig. 3. The value at the time of forming the P-type island area is maintained until the end without being affected by the extraction. For example, if the field oxide film has a thickness of 1 mm or more, the thickness of the field oxide film will hardly change even after a subsequent gate oxidation process of about 1000△, and the impurity concentration of the substrate directly below it will also hardly change. . Therefore, the threshold voltage VTHF of the parasitic MOS transistor is also
It is almost determined when the island region is formed and will not become lower in later steps. The threshold and value voltages of parasitic MOS transistors in island regions formed using conventional manufacturing methods are lowered due to the effect of sucking out impurities in the field oxidation process, etc., and some kind of separation process is essential in the low threshold and value voltage process. On the other hand, the method according to the present invention does not have such concerns and does not require a separation step.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views showing complementary MOS integrated circuits according to the conventional manufacturing method in the order of manufacturing steps, and FIGS. 4 to 6 are complementary MOS integrated circuits showing embodiments of the present invention. FIG. In the figures, the same or corresponding parts are indicated by the same reference numerals. 1 is a silicon substrate, 2 is an oxidation stage, 3 is an island region, and 4 and 4' are field oxide films. Regular figure 1 Heron 2 figure 3 Sei 4 figure 5 Rare figure 6

Claims (1)

[Claims] 1. A step of forming a field oxide film having a plurality of holes spaced apart from each other on one principal surface of a semiconductor substrate having a predetermined conductivity type, introducing selected impurities into the substrate through each of the holes, and introducing a field oxide film into the substrate through each of the holes, respectively opposite to the substrate. A step of forming a conductive type island region, forming a gate insulating film on the central surface of each island region, and forming a gate insulating film on the entire surface of each island region between the gate insulating film and the field oxide film. 1. A method for manufacturing a complementary MOS integrated circuit, comprising the step of introducing selected impurities into a region to form a source region and a drain region, respectively, of the same conductivity type as the substrate.