JPS604630B2 - Phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase detection circuit suitable for use in, for example, an AFC (automatic frequency control) circuit of a television receiver.

For example, a television receiver may require a clock signal synchronized with a horizontal synchronization signal to perform various signal processing.

Such a clock signal generation circuit generally has an AFC (automatic frequency control) circuit configuration using a PLL (phase locked loop) circuit consisting of a VC○ (voltage controlled oscillation circuit), a phase detection circuit, a low-pass filter, etc. . 1st
The figure shows a conventional configuration of a phase detection circuit used in an AFC circuit as described above.

The configuration shown is an oscillation signal S of frequency fH (horizontal scanning frequency) which is the output of VC0 (not shown). A phase comparison is performed between the horizontal synchronizing signal SH and the horizontal synchronizing signal SH separated in horizontal synchronization, and the comparison difference is obtained as a difference in pulse width between the current 1 charging the capacitor Co and the current 12 discharging the capacitor Co. This operation will be explained using FIG. 2. FIG. 2 a shows the oscillation signal S.

shows. In Figure 1, the horizontal synchronizing signal SH is low “L”
level, transistors Q, . turns off, transistors Q,2 turn on, and transistors Q,3,Q,4
The turtle flow lo flows in either direction. At this time, if the oscillation signal So is "L", the transistor Q,3 is turned on, the transistor Q,4 is turned off, and the current is now
flows, and 13=lo. And transistor Q,
5, Q, and 6 constitute a Karen mirror circuit, and when the current amplification factor 8 of transistors Q, 5, Q, and 6 is large, the capacitor C. to charge. This state is shown in FIG. 2b. When the oscillation signal So is at a high "H" level, the transistors Q and 4 are turned on, and the capacitor C becomes 12=lo.
The current is removed from the source to discharge it. This state is shown in FIG. 2d. Horizontal synchronization signal SH is “L” and “H” of oscillation signal So
When this happens, perform both operations explained in Figure 2 b and d,
The result is as shown in FIG. 2c.

Therefore, the capacitor Co is charged and discharged in one horizontal scanning period IH, and the voltage ΔV that changes thereby is expressed by the following equation m.

△V=(1.・t, -12・t2)/C^...
[1} However, L: the time width of the horizontal synchronizing signal SH when the oscillation signal So is "L", etc.: the oscillation signal S.

is the time width of the horizontal synchronizing signal SH when is “H”, and both time widths t
,,t2 has a constant relationship of t, t2=constant.

C^: Capacitance value of capacitor Co Here, ideally, 1, = 12 = lo, so △V is AV = (tl-t2>10/C^ ・--{
2}, and its phase detection characteristics are shown by the solid line A in FIG.

In addition, in Fig. 3, the oscillation signal S of the machine shaft. and horizontal synchronization signal SH. In other words, the slope of the phase detection characteristic is the same when the horizontal synchronizing signal SH is located at the "L" level part of the oscillation signal So and when the horizontal synchronizing signal SH is located at the "H" level part. . However, when the phase detection circuit shown in Fig. 1 is manufactured using an integrated circuit, etc., the P
8 of NP transistors Q, 5, Q, 6 (lateral transistors) is often 4. smaller than the predetermined value or varies, currents 1 and 12 are not equal, and 1 and 12 are not equal. , becomes weaker.

As a result, the phase detection characteristics are as shown by the broken line B in Figure 3, when the horizontal synchronizing signal SH is present in the "L" portion of the oscillation signal So, and when the horizontal synchronizing signal SH is present in the "H" portion of the oscillation signal So. The characteristics of the phase detection characteristics will differ between the two. To explain this below, it is assumed that transistors Q,5 and Q,6 have the same characteristics (base current 18, current amplification factor 3, base-emitter voltage VB8).

Letting the emitter currents of transistors Q, 5, Q, and 6 be IB,,182, respectively, 18,=13-18
......[3'IE2 = 1,10 IB
...... [41 Here, as mentioned above, transistors Q, 5 . Q, 0 in 6 IB,
8 and V88 are equal, so IE,=182, so the currents 13 and 12 are respectively 13:1·1218il, cross. ．． ．． ．． ．． Tanayu 11=13/(10 filial piety)...[6}
becomes.

Therefore, if 13=lo and B>>1, then 1, white 13=
At lo, the phase detection characteristic is as shown by the solid line A in FIG.

However, if 3 is small, 1<13=loo. By the way, △V is △V=(1,.t,-12.t2)/C^=
It is expressed as (11・tl−10・t2)/C^ i71, so as mentioned above, 1. If <lo, the phase detection characteristic will be as shown by the broken line B in FIG.

The AFC circuit operates so that △V = 0, but if there is a part with a different slope in the phase detection characteristic, △V: 0 and the phases of the oscillation signal So and horizontal synchronization signal SH appear to be synchronized. Although it may appear, the oscillation signal So actually deviates from the horizontal synchronization signal SH, resulting in a phase error between the two.

Therefore, it is inconvenient to use an AFC circuit using a phase detection circuit configured as shown in FIG. 1 as a circuit for generating a clock signal synchronized with a horizontal synchronizing signal and serving as a reference signal for various signal processing. This invention was made to deal with the above-mentioned circumstances, and it ensures that the phase detection characteristics are linear.
It is an object of the present invention to provide a phase detection circuit that does not cause problems such as a phase shift between a reference signal and an oscillation signal when the two signals are out of phase.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The part surrounded by the broken line 20 in FIG. 4 is the phase detection circuit.

The transistor Q2 that constitutes this phase detection circuit 20, Q23 and Q23, Q25 and Q26, Q27 and Q2
8 form a differential pair, and constant current source circuits 21, 22, 23, and 24 are connected to the common emitters, respectively. However, the common emits of transistors Q25 and Q26 are also connected to the collector of transistor Q27. The collectors of the transistors QQa, Q24, Q26, and Q are connected to the power supply V2, the collectors of the transistor Q22 are connected to the power supply Va through the resistor R2, and the collector of the transistor Q23 is connected to the resistor R and the diodes D2, D,
22 to the power supply V, and the transistor Q25
The collector of is also connected to the power supply V2 through a resistor and diodes Da and D22. transistor Q22,
The bases of Q24 and Q27 are already connected to the power supply V, and the base of the transistor Q26 is connected to the power supply V. An input terminal 25 for the horizontal synchronizing signal SH is provided at the base of the transistor Q25. Also, transistor Q22
, Q23, Q25 are connected to the bases of NPN transistor Q, PNP transistor Q3o, and PNP transistor Q3, respectively, and the emitters of these three transistors Q29, Q and Q are connected in common, and V
It is connected to the CO circuit 26 and grounded via a capacitor C2.

In the figure, 27 is a frequency divider, and 28 is a pulse generator.
The output terminals 281, 282, and 283 of the pulse generator 28 have an oscillation output So as a test wave pulse as shown in FIG. 1. Pulse P as the second pulse
. , P2 are derived. The operation in the above configuration will be explained.

Oscillation signals So, pulses P, , P shown in Fig. 5 a, b, c
2 are both generated from the output of VC026, so their relative relationship is always constant as shown in the figure. Note that in the following explanation, what is indicated as Vo indicates the base-emitter voltage of a transistor and the forward voltage of a diode. Now, when the pulse P, is derived to the output terminal 282, the transistor Q2, turns on, the transistor Q22 turns off, and the base of the transistor Q29 becomes V^(
voltage of the power supply V2,), and the voltage across the capacitor C2 is raised to (V^-Vo).

Next, when the potential of the output terminal 282 becomes "L", the transistor Q22 is turned on, and the base potential of the transistor Q29 decreases, and the transistor Q29 is turned off. As a result, the voltage across capacitor C is held at (V^-Vo). Next, the output terminal 283
When the pulse P2 is derived, the transistor Q23 is turned on, and the transistor Q3 is turned on. The base potential of capacitor C2. Set the voltage across both ends to (V^-R^・1^-Vo). However, R^ is the resistance value of the resistor 22, and 1^ is the current value of the constant current source circuit 22. After that, the output terminal 283
When becomes "L" level, transistor Q is turned off, the base potential of transistor Qo becomes V^, and this transistor Q3. is off. As a result, the voltage across the capacitor C2 is maintained at (V^-R^·1^-V.). Next, the case where the horizontal synchronizing signal SH is applied to the input terminal 25 will be explained.

The horizontal synchronizing signal SH is applied to the input terminal 25, and the terminal 25
When the level becomes ``H'', transistors Q25, Q,
turns on, lowering the voltage across capacitor C2 to a constant voltage. Next, when the level of the terminal 25 becomes "L", the base potential of the transistor Q becomes V^, the transistor Q3 is turned off, and the potential across the capacitor Ca at that time is held. There are two types of voltages set in the capacitor C2 by this horizontal synchronizing signal SH.

That is, one case is when the horizontal synchronizing signal SH is applied when the oscillation signal So derived to the output terminal 281 is at the "H" level. In this case, transistor Q28 is on and transistor Q27 is off, so the base potential of transistor Q is (V^-2VD-R8・1
8). However, RB is the resistance value of the resistor R, and IB is the current value of the constant current source circuit 23. Therefore, the voltage across the capacitor C2 is (V^-2V. 1 RB/IB 10 V.
), that is, (V^1V.1R8・IB). One more
The first case is when the horizontal synchronizing signal SH is applied when the oscillation signal So is at the "L" level.

In this case, transistor Q28 is off, transistor Q
Injury is on. Therefore, the base potential of transistor Q8 is [V^-2Vo-RB・(IB1lc)]
Therefore, the voltage across the capacitor C2 becomes [V^-Vo-R8 (180 lc)]. However, lc is the current value of the constant current source circuit 24. Here, R^=R8=Ro, 1
^=IB=lc=lo, each transistor Q29
, Q3o, Q3, set and hold the voltage across the capacitor C2, when using the transistor Q29 (V^-V).

), by transistor Qo (V^-Vo-Ro・
1. ), by transistor Q3 (V^-Vo-
R.・1. ) or (V^1V.-2・R.・1.). Here, if (V^-Vo-Ro・lo) is VR, the voltage across the capacitor C2 is 3 values (VR+Ro・lo ),
(VR) and (VR-Ro·lo). As shown in the figure, the waveform of the voltage across the capacitor C differs depending on the phase difference between the oscillation signal So and the horizontal synchronizing signal SH, and this causes the average voltage during the IH period to differ. Figure 5 d
As the horizontal synchronizing signal SH moves from the pulse P position to the pulse P2 position (when the phase difference between the pulse P and the horizontal synchronizing signal SH is within 1800), the voltage across the phantom capacitor C becomes (VR+Ro・1.

) becomes wider, and the average voltage across the capacitor C2 gradually increases. Then, as shown in FIG. 5e, when the phases of pulse P2 and horizontal synchronizing signal SH match, (VR+Ro・1.) and (VR−R.・lo)
The width becomes the same, and the average voltage drops rapidly. Then, as shown in FIG. 5f, the horizontal synchronizing signal SH is pulsed P2.
As the pulse P moves from position to position (when the phase difference between pulse P and horizontal synchronizing signal SH is 180 degrees or more), (V
R-Vo.lo) gradually becomes narrower, and the average voltage gradually increases from the lowest value VR. The average voltage obtained by smoothing the voltage across the capacitor C2 in this way is the horizontal synchronizing signal S1 and the oscillation signal S. Since the phase changes gradually according to the phase difference between the FIG. 6 shows the phase detection characteristics of the phase detection circuit 20 of FIG. 4. In the figure, the vertical axis ΔV represents the average voltage across the capacitor C2, and the horizontal axis 8' represents the phase (time) difference tQ between the oscillation signal So and the horizontal synchronizing signal SH. Point a in the figure is a point where the oscillation signal So and horizontal synchronization signal SH are deviated by 180o (m radians), and point b in the figure is a point where they are deviated by -180o (bamboo radians), and the time is approximately 32 sec. This corresponds to the deviation of This embodiment described in detail above has the following effects.

Since the transistors Q29 and Q are emitter hololocks, the output impedance is low, the on/off operation is quick, and a desired voltage can be instantaneously set and maintained across the capacitor C2. Also, when converting the circuit into an IC, the current values 1^, 18, lc and the resistance values R^, R
B can be set to a desired value with high accuracy. From the above points, the phase detection circuit configured as shown in Fig. 4 can provide linearity to its phase detection characteristics over the IH period, and even if the average voltage of the capacitor C reaches V6, the horizontal synchronization signal cannot be detected. There is no problem that the phases of SH and oscillation signal So are still out of phase. Further, according to the configuration shown in FIG. 4, it is possible to provide a single-ended output and reduce the number of pins of an IC, etc. As described above, the present invention provides a phase detection circuit in which the phase detection characteristic has reliably linearity and there is no problem such as a phase shift between the reference signal and the oscillation signal when the two signals are synchronized. can do.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional phase detection circuit, Figures 2 a to d are signal waveform diagrams of various parts to explain the operation of the circuit in Figure 1, and Figure 3 is a phase diagram of the circuit in Figure 1. Detection characteristic diagram, FIG. 4 is a circuit diagram showing one embodiment of the phase detection circuit according to the present invention, FIGS. FIG. 6 is a phase detection characteristic diagram of the circuit of FIG. 4. Q2, to Q24...transistors, 21 to 24.
...constant current source circuit, Ra to R23...resistance, D illusion,
D2...diode, V2, to V24...power supply, C common...capacitor. Figure 1 Figure 2 Figure 3 Figure 6 Figure 4 Figure 5

Claims (1)

[Claims] 1. In a phase detection circuit in a PLL circuit that performs phase detection between a reference signal and an oscillation output of a voltage control oscillation circuit and uses this detection output to control the frequency of the oscillation output, the voltage control oscillation circuit A first output terminal that derives a test wave pulse corresponding to the output of the test wave pulse, a second output terminal that derives a first pulse corresponding to the leading edge of the test wave pulse, and a trailing edge of the test wave pulse. a pulse generator having a third output terminal from which a corresponding second pulse is derived; a capacitor connected to the voltage control terminal of the voltage controlled oscillation circuit; The first
a first differential switch that switches in response to a pulse from the reference voltage source, charges the capacitor to a first voltage value that depends on the voltage value of the reference voltage source when conductive, and holds this charging voltage when cut off; It switches in response to the second pulse delivered to the third output terminal of the first
a second differential switch that charges the capacitor to a second potential that is lower than the voltage value of the pulse generator and holds this charging voltage when cut off; a phase determination means to which a test wave pulse is applied, a synchronization signal which is a reference phase signal is applied to the other input terminal, and a current flowing through the load is controlled according to the polarity of the test wave pulse and the polarity of the synchronization signal; A phase detection circuit characterized by comprising a control switch driven by the phase discrimination means and controlling the charging voltage of the capacitor.