JPS6046549B2 - Gate turn-off thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate turn-off thyristor (hereinafter abbreviated as a GTO thyristor) that operates on and off depending on the polarity of the gate current, and particularly relates to a gate turn-off thyristor (hereinafter abbreviated as a GTO thyristor) which operates on and off depending on the gate current polarity. The present invention relates to a GTO thyristor having a structure in which a low-resistance gate layer is formed and brought out to the outside as a gate electrode.

The conventional structure of this type of GTO thyristor is shown in FIG.
In a normal three-junction thyristor structure with four layers of P, , N, , Po, and No, a low-resistance P1 layer is embedded in the center of the Po layer, and an externally drawn gate electrode G is electrically connected to this P'' layer. connected.

As shown in the figure, the planar shape of the low resistance layer P1 has a structure extending from the center toward the periphery in a trochoidal curve (or radial shape), and a manufacturing process diagram is shown in FIG.
In Figure 2, an N-type 5 shown in a is formed on both sides of the wafer 1 to form P layers 2 and 3, and an oxide film 4 is formed on the surfaces of the OP layers 2 and 3. A part of the mirror-polished cathode side oxide film 4 is removed in a shape in which the low-resistance gate layer P is to be buried, and d) B is diffused into the P layer 2 by a thermal diffusion method to form the P1 layer 5. After removing the oxide film 4 by etching with hydrofluoric acid, a P layer 6 is formed by epitaxial growth on the surfaces of the fNP layer 2 and the Pf layer 5.
, to form the oxide film 7, the cathode side oxide film 7 is etched leaving the center and peripheral parts, i) phosphorus is diffused into the part to form the N layer 8, and further the oxide film 9 is formed.
Next, the anode side oxide film 7 is removed and gold is diffused from the kNP layer 3 side, and the cathode side oxide film 7 is removed and the central part is
Dig down to the f layer, finally P layer 3, N layer 8, P1 layer 5
An electrode is formed on which alloy and N are vapor-deposited.

In such a conventional GTO thyristor, as shown in FIG. 3, the buried P1 layer is diffused into the P layer (Out"Glffusion) during the phosphorus diffusion process of forming the N layer on the cathode side.
The substantial distance d between the first layer and the N layer is reduced.

This distance d is related to the gate-cathode drop that occurs when the depletion layer P1 spread in the P epitaxial growth layer 6 is reached, and by increasing d, the gate-cathode breakdown voltage can be increased. On the other hand, the increase in distance d is Ni, P2, N
The current amplification factor of the two transistors decreases, and the turn-off gain decreases. The present invention has been made in view of the above problems, and an object of the present invention is to provide a thyristor structure that has a large gate-cathode breakdown voltage and can avoid a decrease in turn-off gain.

In the present invention, the thickness of the P epitaxial growth layer sandwiched between the low-resistance gate layer P+ and the N2 layer is such that the N2 layer is made uneven so that the portion facing the low-resistance gate layer P+ is thicker than the other portions. The effective distance d between the P+ layer and the N2 layer is increased or the thickness of the P2 layer, which functions as a transistor, is decreased.

FIG. 4 shows an embodiment of the present invention, and the difference from FIG. 1 is that the N2 layer has a recessed portion facing the P+ layer.

An enlarged view of the N2 layer portion is shown in FIG. As is clear from the figure, the thickness of the N2 layer in the portion facing the P+ layer is from d to D. The breakdown voltage between the gate and cathode increases, and the thickness of the other parts becomes the same as in Fig. 3, so that Nl, P2, N
The current amplification factors of the two transistors are equivalent. In other words, it has the same gate-cathode breakdown voltage as the conventional one and has an improved turn-off gain. FIG. 6 shows another embodiment of the present invention, in which the low-resistance gate layer P+ is located deep into the recessed portion of the N2 layer.

In other words, this is a structure in which the portions of the N2 layer that do not face the P+ layer are deeply diffused. In this case as well, the same effects as in the embodiment described above can be achieved. FIG. 7 shows a manufacturing process diagram of a thyristor having the structure shown in FIG. 4 or FIG. 6, and shows the steps I and j in FIG. 2. That is, the etching of the cathode side oxide film 7 is performed using P.
After forming the N layer by phosphorus diffusion, leaving the part facing the + layer, forming the oxide film 7A, b1 etching leaving the center and peripheral parts of the oxide film 7A, and C1 diffusing phosphorus again to form the N layer with an uneven structure. After that, the procedure is the same as that shown in FIG. 2k. As described above, the thyristor structure according to the present invention can improve the breakdown voltage between the gate and cathode or increase the turn-off gain by substantially increasing the distance between the low resistance gate layer P+ and the N2 layer. Furthermore, the N2 layer can be diffused deeper than in the conventional structure, which increases the radius of curvature of the N2 layer etching, reduces electric field concentration, and increases the withstand voltage at the edge. In addition, the allowable rising slope of forward voltage (D
v/Dt characteristics) are improved. This is because the injection efficiency of electrons from the recessed portion of the cathode to the P base layer is reduced. As an experiment for the structure of the present invention, the resistance of the P+ buried layer formed by diffusing boron B with a surface concentration of 1×1 Cf20 and the epitaxially grown layer P sandwiched between this P+ layer and the cathode N2 layer was set to 15Ω-Cm. , base width d is 10μ
The withstand voltage between the gate and cathode is 5 in the conventional structure when
0 to 150■, but with the structure of the present invention, it was 100 to 3
00V, and the Dv/Dt characteristics were also improved by about twice or more.

[Brief explanation of drawings]

Figure 1 is a conventional GTO thyristor structure diagram, Figure 2 is a diagram of the structure of a conventional GTO thyristor.
Figure 3 is a diagram for explaining the conventional structure, Figure 4 is a structural diagram showing an embodiment of the present invention, Figure 5 is an enlarged view of the main part of Figure 4, and Figure 6 is a diagram for explaining the conventional structure. The figure is a structural diagram showing another embodiment of the present invention, and FIG. 7 is a manufacturing process diagram of the main part of the structure of the present invention.

Claims (1)

[Claims] 1 P_1, N_1, P with a structure in which a low resistance gate layer P^+ is embedded in the base layer P_2 forming the gate layer, and this low resistance gate layer P^+ is drawn out to the outside as a gate electrode.
In the gate turn-off thyristor consisting of _2 and N_2 layers, the thickness of the base layer P_2 sandwiched between the low-resistance gate layer and the N_2 layer is such that the portion facing the low-resistance gate layer is thicker than the other portions. A gate turn-off thyristor characterized by a structure in which N_2 has unevenness.