JPS6046825B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS6046825B2 JPS6046825B2 JP6364778A JP6364778A JPS6046825B2 JP S6046825 B2 JPS6046825 B2 JP S6046825B2 JP 6364778 A JP6364778 A JP 6364778A JP 6364778 A JP6364778 A JP 6364778A JP S6046825 B2 JPS6046825 B2 JP S6046825B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysiloxane
- semiconductor device
- wiring
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229920001296 polysiloxane Polymers 0.000 claims description 27
- -1 polysiloxane Polymers 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 21
- 230000007797 corrosion Effects 0.000 description 12
- 238000005260 corrosion Methods 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000009832 plasma treatment Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000010306 acid treatment Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BYFGZMCJNACEKR-UHFFFAOYSA-N aluminium(i) oxide Chemical compound [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- KVBCYCWRDBDGBG-UHFFFAOYSA-N azane;dihydrofluoride Chemical compound [NH4+].F.[F-] KVBCYCWRDBDGBG-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000000325 methylidene group Chemical group [H]C([H])=* 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特に多層配線
構造における上層配線施設面の表面清浄法を導入した多
層配線型半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a multilayer wiring type semiconductor device that introduces a surface cleaning method for an upper wiring facility surface in a multilayer wiring structure.
通常、層間絶縁膜を介して多層金属膜配線を施す時、上
層と下層の導通領域、即ち、スルー・ホール部において
、該スルー、ホール部の深さが深い場合に上層配線が断
線不良を生じる。Normally, when performing multilayer metal film interconnection through an interlayer insulating film, disconnection occurs in the upper layer interconnection in the conduction area between the upper layer and the lower layer, that is, in the through hole section, if the depth of the through hole section is deep. .
従来、上記改善策として、液体状ポリキサン液を該半導
体基板上に塗布施設して被膜を作り、該被膜の腐食速度
が早い特性を利用して上記スルー・ホール部の層間絶縁
膜を傾斜腐食して該スルー・ホール部段差を小さくし、
上層配線の断線を防いている。しカルながら、これらの
方法によると、スルー・ホール部を開孔する時に用いた
ホトレジスト膜が該ポリシロキサン膜に被着した時、ホ
トレジスト膜(あるいは該ホトレジスト膜の密着性向上
用に用いるヘキサ、メチレン・ジアシン膜)中の有機系
物質が反応して表面層を異質にし、上記配線用金属膜を
付着させる前の表面処理を不完全にして該金属膜の密着
性を劣化させて微小配線回路の剥離断線やボンディング
部の剥離不良を生じた。本発明の目的は上記の欠点を除
去し、ポリシロキサン膜を用いた表面の清浄化を施して
上層金属膜の密着性を向上させることにある。本発明の
特徴は、下層配線上の層間絶縁膜表面にポリシロキサン
膜を被着させ、所定領域上にホトレジスト膜マスクを設
けて該層間絶縁膜のスルー・ホール部を開孔させる工程
と、上記ホトレジスト膜を除去して後ポリシロキサン膜
表面上に残存するポリシロキサン膜の変質層を荷電粒子
雰囲気に照射して除去する工程と、前記ポリシロキサン
膜の全量を化学的腐食除去する工程と、該スルー・ホー
ル部に接して上層配線を設ける工程とを含む半導体装置
の製造方法である。Conventionally, as a measure to improve the above, a liquid polyxane solution is applied onto the semiconductor substrate to form a film, and the interlayer insulating film in the through-hole portion is etched at an angle by utilizing the property of the film to corrode quickly. to reduce the step difference in the through-hole part,
Prevents disconnection of upper layer wiring. However, according to these methods, when the photoresist film used to open the through-hole portion adheres to the polysiloxane film, the photoresist film (or the hexafluoride used to improve the adhesion of the photoresist film) The organic substances in the methylene/diacine film) react to make the surface layer heterogeneous, and the surface treatment before attaching the metal film for wiring is incomplete, causing the adhesion of the metal film to deteriorate, resulting in micro wiring circuits. Peeling and disconnection of the wire and defective peeling of the bonding part occurred. An object of the present invention is to eliminate the above-mentioned drawbacks and improve the adhesion of the upper metal film by cleaning the surface using a polysiloxane film. The features of the present invention include the steps of depositing a polysiloxane film on the surface of the interlayer insulating film on the lower wiring, providing a photoresist film mask on a predetermined area, and opening a through hole in the interlayer insulating film; a step of removing the altered layer of the polysiloxane film remaining on the surface of the polysiloxane film after removing the photoresist film by irradiating it with a charged particle atmosphere; and a step of removing the entire amount of the polysiloxane film by chemical corrosion; This method of manufacturing a semiconductor device includes a step of providing an upper layer wiring in contact with a through-hole portion.
本発明によると、スルー・ホール部の層間絶縁膜を傾斜
腐食させるに用いたポリシロキサン膜が”ホトレジスト
膜と接触して表面変質するが、例えば酸素や窒素等のガ
スプラズマ(荷電粒子状態)雰囲気で除去することによ
り、化学的腐食液の濡れ状態が良くなり、且つ腐食速度
が安定化して該ポリシロキサン膜の均一除去が達成でき
、上層配線を施設した時の密着性を向上させ、該配線の
剥離不良、ボンディング剥離不良を解消させることにな
る。According to the present invention, the polysiloxane film used for the inclined corrosion of the interlayer insulating film in the through-hole portion comes into contact with the photoresist film and undergoes surface deterioration. By removing the polysiloxane film, the wettability of the chemical corrosive solution is improved, the corrosion rate is stabilized, and uniform removal of the polysiloxane film can be achieved, which improves the adhesion when installing the upper layer wiring, and improves the wettability of the chemical corrosion solution. This will eliminate defects in peeling and bonding defects.
次に本発明について図面を参照して説明する。Next, the present invention will be explained with reference to the drawings.
尚、説明の都合上、半導体装置を構成する一つのスルー
・ホール部領域を用いて、A1膜の二層配線構造の場合
で示した。第1図〜第7図は本発明の一実施例の多層配
線型半導体装置の製造方法を示した断面図であり、シリ
コン基板1と主面絶縁膜2(例えばSiO2膜やSl3
N4膜)と不純物拡散素子領域3を有する半導体基板に
対して、第1層目配線としてのA1膜4と配線間絶縁膜
として多孔質Al.O3膜5を設け、A1膜上に薄い無
孔質Al.O3膜6に第1スルー・ホール部7を開孔し
、層間絶縁膜として例えば気相成長SlO3膜8を設け
る。For convenience of explanation, a case of a two-layer wiring structure of A1 film is shown using one through-hole region constituting the semiconductor device. 1 to 7 are cross-sectional views showing a method of manufacturing a multilayer wiring type semiconductor device according to an embodiment of the present invention.
N4 film) and an impurity diffusion element region 3, an A1 film 4 as a first layer wiring and a porous Al. An O3 membrane 5 is provided, and a thin non-porous Al. A first through-hole portion 7 is opened in the O3 film 6, and a vapor-phase grown SlO3 film 8, for example, is provided as an interlayer insulating film.
層間絶縁膜はSi3N4膜、ポリイシド膜の材質、スパ
ッタ等の析出方法に依つてもさしつかえない(第1図)
。次に該主面にポリシロキサン膜9を設ける。ポリシロ
キサン膜は液体状のものを塗布して被膜とし、150〜
200゜Cの温度でベークして形成する(第2図)。続
いて、前記第1のスルー・ホール部7のパターンに合せ
てホトレジスト膜10のパターンを設ける(第3図)。
更に、該ホトレジスト膜10をマスクにしてホトレジス
ト膜開孔部のポリシロキサン膜9と層間絶縁膜としての
SlO2膜8を例えば弗酸沸化アンモニウム混液で腐食
除去して、下地のA1膜4面を露出させて第2スルー・
ホール部の開孔処理を終える。この時SiO2膜8の開
孔端部は上層のポリシロキサン膜の腐食速度が速いので
傾斜部11を形成する(第4図)。次に前記ホトレジス
ト膜10を除去すると、ポリシロキサン膜9の表面にホ
トレジスト膜と接触したために生じた変質層12が残る
(第5図)。この一状態で、酸素又は窒素プラズマ処理
する。例えば1〜0.1t0rr.で02ガスをプラズ
マ発生容器内に入れ、200W,rfパワーで02プラ
ズマ(荷電粒子状態)にし、該半導体装置基板を一定時
間照射して上記変質層を除去する(第6図)。しかる後
、例.えば沸酸系処理液でポリシロキサン膜9を均一除
去し、表面を清浄化して別のA1膜13を設けて上層配
線とし、A1膜4−A1膜13の二層配線型半導体装置
を形成する(第7図)。上記実施例によると、スルー・
ホール部の傾斜・腐食のために用いたポリシロキサン膜
がホトレジスト膜と接触したために組成変質した表面層
をプラズマ処理法で除去できるため、上層配線を施設す
る時の化学的腐食液がポリシロキサン膜とよく濡れ、か
つ均一な腐食速度を示すので該スルー・ホール部の下層
AI膜4を過剰腐食することがなく、該上層AI膜の配
線密着性を保持し、ボンディング時のAl膜剥離不良を
防止し、更には、該スルー・ホール部での断線不良をも
防止させる。The interlayer insulating film can be used depending on the material of the Si3N4 film or polyamide film, and the deposition method such as sputtering (Figure 1).
. Next, a polysiloxane film 9 is provided on the main surface. The polysiloxane film is made into a film by applying a liquid, and the film is made from 150~
It is formed by baking at a temperature of 200°C (Figure 2). Subsequently, a pattern of the photoresist film 10 is provided in accordance with the pattern of the first through-hole portion 7 (FIG. 3).
Furthermore, using the photoresist film 10 as a mask, the polysiloxane film 9 in the opening of the photoresist film and the SlO2 film 8 as an interlayer insulating film are etched away with, for example, an ammonium hydrofluoride fluoride mixture, and the four surfaces of the underlying A1 film are removed. Expose and pass through the second
Finish the hole opening process. At this time, the opening end of the SiO2 film 8 forms a sloped part 11 because the upper polysiloxane film corrodes at a high rate (FIG. 4). Next, when the photoresist film 10 is removed, a degraded layer 12 caused by contact with the photoresist film remains on the surface of the polysiloxane film 9 (FIG. 5). In this state, oxygen or nitrogen plasma treatment is performed. For example, 1 to 0.1t0rr. Then, 02 gas is put into a plasma generation container and 02 plasma (charged particle state) is generated with 200 W and RF power, and the semiconductor device substrate is irradiated for a certain period of time to remove the above-mentioned altered layer (FIG. 6). After that, e.g. For example, the polysiloxane film 9 is uniformly removed using a hydrofluoric acid treatment solution, the surface is cleaned, and another A1 film 13 is provided as an upper layer wiring, thereby forming a two-layer wiring type semiconductor device of A1 film 4-A1 film 13. (Figure 7). According to the above embodiment, through-
The surface layer whose composition has changed due to the contact of the polysiloxane film used for tilting and corroding the hole with the photoresist film can be removed by plasma treatment, so the chemical etchant used when installing the upper layer wiring can be removed from the polysiloxane film. Because it wets well and exhibits a uniform corrosion rate, the lower layer AI film 4 in the through-hole area is not excessively corroded, the wiring adhesion of the upper layer AI film is maintained, and defective Al film peeling during bonding is prevented. This also prevents disconnection defects at the through-hole portion.
第8図はポリシロキサン膜被着させ、各温度て加熱処理
を0.5時間処理した時の表面にホトレジスト膜を付着
させ、後に該ホトレジスト膜を除去して弗酸系処理液て
腐食処理した時の除去時間を示したものである。Aは上
記状態の酸素プラズマ処理を経ない時のものであり、腐
食時間が長く、且つ不均一な結果を示している。一方、
Bは酸素プラズマ処理を経たものであり、腐食時間が短
かく、均一な結果を示している。即ち、Bはホトレジス
ト膜に接したポリシロキサン膜の表面が酸素”プラズマ
処理で安定化したことを現しているものてあり、従つて
、Al膜を上層配線する時の弗酸処理を短時間で行える
ため、前述したようにスルー・ホール部の過剰腐食が防
止できるようになる。Figure 8 shows a photoresist film attached to the surface after a polysiloxane film was deposited and heat treated at each temperature for 0.5 hours, after which the photoresist film was removed and a corrosion treatment was performed using a hydrofluoric acid treatment solution. This shows the removal time of the time. A is a sample obtained without oxygen plasma treatment under the above conditions, and shows a long corrosion time and non-uniform results. on the other hand,
B was subjected to oxygen plasma treatment, and showed a short corrosion time and uniform results. In other words, B indicates that the surface of the polysiloxane film in contact with the photoresist film has been stabilized by oxygen plasma treatment, and therefore the hydrofluoric acid treatment when wiring the upper layer of the Al film can be completed in a short time. This makes it possible to prevent excessive corrosion of the through-hole portion as described above.
第1図乃至第7図は本発明の一実施例の多層配線型の半
導体装置の製造方法を工程順に示した断面図であり、第
8図はポリシロキサン膜の加熱温度と腐食速度の関係を
示した図である。
尚、図において、1・・・・・シリコン基板、2・・・
SjO2膜、3・・・・・不純物拡散素子領域、4・・
・・・・一層目AI膜、5・・・・・・多孔質Al2O
3膜、6・・・・・・無孔質Al2O3膜、7・・・・
・・スルー・ホール部、8・・・・・層間SiO2膜、
9・・・・・ポリシロキサン膜、10・・・・・・ホト
レジスト膜、11・・・・・・スルー●ホール部SiO
2膜端の傾斜部、12・・・・ポリシロキサン膜の変質
層、13・・・・二層目A1膜、A線・・・・・・表面
変質層を有するポリシロキサン膜の腐食状態、B線・・
・・プラズマ処理後のポリシロキサン膜の腐食状態であ
る。1 to 7 are cross-sectional views showing the manufacturing method of a multilayer wiring type semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 8 shows the relationship between the heating temperature and corrosion rate of the polysiloxane film. FIG. In addition, in the figure, 1... silicon substrate, 2...
SjO2 film, 3... impurity diffusion element region, 4...
...First layer AI film, 5...Porous Al2O
3 membrane, 6... non-porous Al2O3 membrane, 7...
...Through hole part, 8...Interlayer SiO2 film,
9...Polysiloxane film, 10...Photoresist film, 11...Through hole part SiO
2 Slanted part at the end of the membrane, 12... Altered layer of the polysiloxane film, 13... Second layer A1 film, A line... Corrosion state of the polysiloxane film having a surface altered layer, B line...
...This is the corrosion state of the polysiloxane film after plasma treatment.
Claims (1)
被着させ、所定領域上にホトレジスト膜マスクを設けて
該層間絶縁膜にスルー・ホール部を開孔させる工程と、
上記ホトレジスト膜を除去して後、上記ポリシロキサン
膜表面上に荷電粒子を照射する工程と、前記ポリシロキ
サン膜を化学的に除去する工程とを含むことを特徴とす
る半導体装置の製造方法。1. A step of depositing a polysiloxane film on the surface of the interlayer insulating film on the lower wiring, providing a photoresist film mask on a predetermined area, and opening a through-hole portion in the interlayer insulating film;
A method for manufacturing a semiconductor device, comprising the steps of: after removing the photoresist film, irradiating the surface of the polysiloxane film with charged particles; and chemically removing the polysiloxane film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6364778A JPS6046825B2 (en) | 1978-05-26 | 1978-05-26 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6364778A JPS6046825B2 (en) | 1978-05-26 | 1978-05-26 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54154982A JPS54154982A (en) | 1979-12-06 |
| JPS6046825B2 true JPS6046825B2 (en) | 1985-10-18 |
Family
ID=13235342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6364778A Expired JPS6046825B2 (en) | 1978-05-26 | 1978-05-26 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6046825B2 (en) |
-
1978
- 1978-05-26 JP JP6364778A patent/JPS6046825B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54154982A (en) | 1979-12-06 |
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