JPS6047760B2 - High-speed simultaneous multilayer wiring electronic component mounting method - Google Patents
High-speed simultaneous multilayer wiring electronic component mounting methodInfo
- Publication number
- JPS6047760B2 JPS6047760B2 JP50078925A JP7892575A JPS6047760B2 JP S6047760 B2 JPS6047760 B2 JP S6047760B2 JP 50078925 A JP50078925 A JP 50078925A JP 7892575 A JP7892575 A JP 7892575A JP S6047760 B2 JPS6047760 B2 JP S6047760B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- electronic component
- component mounting
- mounting method
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 本発明は多層配線と電子部品の実装に関する。[Detailed description of the invention] The present invention relates to multilayer wiring and mounting of electronic components.
従来この種の多層配線と電子部品の実装は平面的であり
、しかも個々、別々に行なわれてきた。この場合、多層
配線は平面的なため、各配線層を別々に重ねることによ
りなされてきたが、各配線層同士の位置合せに時間がか
かり、電子部品の実装も、多層配線を別々に行うために
、時間がかかる欠点があつた。本発明の目的は上述の従
来方法の欠点を除去した多層配線、及び電子部品自装方
法を提供することにある。Conventionally, this type of multilayer wiring and electronic component mounting has been done on a two-dimensional basis and individually and separately. In this case, since multilayer wiring is planar, it has been done by stacking each wiring layer separately, but it takes time to align each wiring layer, and mounting of electronic components has to be done separately. However, it had the disadvantage of being time consuming. An object of the present invention is to provide a multilayer wiring and a self-mounting method for electronic components, which eliminates the drawbacks of the above-mentioned conventional methods.
この明の多層配線及び、電子部品実装方法は多層配線を
容易にし、多層配線と電子部品実装を同時に、しかも高
速に行うことを特徴とする。The multilayer wiring and electronic component mounting method of this invention is characterized by facilitating multilayer wiring and simultaneously performing multilayer wiring and electronic component mounting at high speed.
第1図は印刷された配線を有し、しかも電子部品を実装
されたフィルムの平面図である。第1図において、フィ
ルム1は絶縁性の物質でできており、配線2と電子部品
3を有している。具体的には、ポリイミドやマイラ−の
柔軟性絶縁フィルムに、銅箔を一面に接合ししたものに
、プリント基板の製造などで一般に周知の技術である感
光性レジストと所要のパターンを有するマスクにより露
光現像し、エッチングによつて配線パターンを形成、さ
らに電子部品3は、フィルムキャリア方式として、一般
に周知の方法でボンディングして生産される。FIG. 1 is a plan view of a film having printed wiring and mounted with electronic components. In FIG. 1, a film 1 is made of an insulating material and has wiring 2 and electronic components 3. Specifically, a flexible insulating film made of polyimide or mylar is bonded with copper foil on one surface, and then a photosensitive resist and a mask with the required pattern are used, which is a technology commonly known in the manufacture of printed circuit boards. A wiring pattern is formed by exposure and development and etching, and the electronic component 3 is produced by bonding using a generally known method using a film carrier method.
第2図は空銅部4、とくぼみ5を有する円筒6の斜視図
である。FIG. 2 is a perspective view of a cylinder 6 having an empty copper portion 4 and a recess 5. FIG.
第2図において、円筒6は熱伝導性のよい金属等の物質
から構成されている。具体的には、パイプ状の金属材料
を切削加工または、鋳造などにより生産される。第3図
は本発明の第1の実施例を示す斜視図である。In FIG. 2, the cylinder 6 is made of a material such as metal that has good thermal conductivity. Specifically, it is produced by cutting or casting a pipe-shaped metal material. FIG. 3 is a perspective view showing the first embodiment of the present invention.
第3図において、配線を有し、しかも電子部品3を実装
させた。フィルム1が円筒6に巻きつけられつつあり、
多層配線と電子部品の実装が同時に連続的になされつつ
ある。この際、円筒6の径、フィルム1の上の配線2や
電子部品3の位置さらにはフィルム1の厚みなどの精度
は、多層化する配線層間で必要となる精度内に管理され
る必要があるが、ここで、通常のフィルムキャリヤで実
施されているのと同様のスプロケットホール(図示せず
)をフィルムに形成し、円筒6にそのスプロケットホー
ルに対応する位置にピンまたは突起(図示せず)を形成
し、それらを、はめ込むようにすることによつて容易に
位置出しが可能となる。In FIG. 3, wiring is provided and electronic components 3 are mounted. Film 1 is being wrapped around cylinder 6,
Multilayer wiring and electronic component mounting are being carried out simultaneously and continuously. At this time, the accuracy of the diameter of the cylinder 6, the position of the wiring 2 and electronic components 3 on the film 1, and the thickness of the film 1 must be controlled within the accuracy required between the multilayer wiring layers. However, now a sprocket hole (not shown) similar to that implemented in conventional film carriers is formed in the film, and a pin or projection (not shown) is placed on the cylinder 6 at a position corresponding to the sprocket hole. By forming these and fitting them into each other, easy positioning becomes possible.
このように長尺のフィルム上でパターンの形成、電子部
品のボンディングを行ない、金属などの円筒に巻きつけ
るといつた一連の流れによつて製造可能であるので、自
動化が容易で大量生産が可能になり、安価にできる。In this way, it can be manufactured through a series of steps, such as forming a pattern on a long film, bonding electronic components, and winding it around a cylinder made of metal, etc., so automation is easy and mass production is possible. and can be done inexpensively.
第4図は第3図におけるA−Bに従つた拡大断面図であ
る。FIG. 4 is an enlarged sectional view taken along line AB in FIG. 3.
第4図では、電子部品3は円筒6のくぼみ5に接合され
、配線2は多層化されており、各層の配線2間は絶縁性
を有するフィルム1て絶縁されている。なお各配線層間
の連絡はスルホール7によつてなされている。第5図は
第2図の実施例を示す斜視図である。In FIG. 4, the electronic component 3 is joined to the recess 5 of the cylinder 6, the wiring 2 is multilayered, and the wiring 2 of each layer is insulated by an insulating film 1. Note that communication between each wiring layer is provided by through holes 7. FIG. 5 is a perspective view showing the embodiment of FIG. 2.
第5図ではフィルム1が断面が六角形のブロック体8に
巻きつけられて実装されている。なお、この他の多角形
ブ七ツク体にも実装可能である。In FIG. 5, the film 1 is wound and mounted around a block 8 having a hexagonal cross section. Note that it is also possible to implement other polygonal blocks.
本発明の実装方法を用いると、多層配線と電子部品の実
装を容易に、高速に行うことができる。また本発明の実
装方法は高速に、大量に製造する必要のある電子装置、
例えば電子計算機の電子装置に特に有効に適用できる。
図面の簡単な説明第1図は印刷された配線と実装された
電子部品を有するフィルムの平面図、第2図はくぼみを
有する円筒の斜視図、第3図は本発明の第1の実施例を
示す斜視図、第4図は、第3図のA−Bに従つた拡大断
面図、第5図は第2図の実施例を示す斜視図である。By using the mounting method of the present invention, multilayer wiring and electronic components can be mounted easily and at high speed. Furthermore, the mounting method of the present invention can be applied to electronic devices that need to be manufactured in large quantities at high speed;
For example, it can be particularly effectively applied to electronic devices such as computers.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of a film with printed wiring and mounted electronic components, FIG. 2 is a perspective view of a cylinder with a recess, and FIG. 3 is a first embodiment of the invention. FIG. 4 is an enlarged sectional view taken along line AB in FIG. 3, and FIG. 5 is a perspective view showing the embodiment of FIG. 2.
第1図から第5図までにおいて、参照数字1はフィルム
、参照数字2は配線、参照数字3は電子部品、参照数字
4は空銅部、参照数字5はくぼみ、参照数字6は円筒、
参照数字7はスルホール、参照数字8は六角形ブロック
体をそれぞれ示す。In Figures 1 to 5, reference numeral 1 is a film, reference numeral 2 is wiring, reference numeral 3 is an electronic component, reference numeral 4 is an empty copper part, reference numeral 5 is a recess, reference numeral 6 is a cylinder,
Reference numeral 7 indicates a through hole, and reference numeral 8 indicates a hexagonal block.
Claims (1)
電子部品を実装されたフィルムを、円筒や、多角形のブ
ロック体に巻きつけることによつて、多層配線と多数個
の電子部品実装を、行うことを特徴とする実装方法。1. Multilayer wiring and mounting of a large number of electronic components can be achieved by wrapping a film with pre-printed wiring and a large number of electronic components mounted around a cylinder or polygonal block. An implementation method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50078925A JPS6047760B2 (en) | 1975-06-24 | 1975-06-24 | High-speed simultaneous multilayer wiring electronic component mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50078925A JPS6047760B2 (en) | 1975-06-24 | 1975-06-24 | High-speed simultaneous multilayer wiring electronic component mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS523161A JPS523161A (en) | 1977-01-11 |
| JPS6047760B2 true JPS6047760B2 (en) | 1985-10-23 |
Family
ID=13675428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50078925A Expired JPS6047760B2 (en) | 1975-06-24 | 1975-06-24 | High-speed simultaneous multilayer wiring electronic component mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047760B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5415984A (en) * | 1977-07-06 | 1979-02-06 | Fuji Shoji | Method of forming airrinntire |
| JPS5884749A (en) * | 1981-11-13 | 1983-05-20 | Bridgestone Corp | Manufacture of tire |
| CN1313022C (en) * | 2003-09-12 | 2007-05-02 | 赵明伟 | Alpha starch rice production method |
-
1975
- 1975-06-24 JP JP50078925A patent/JPS6047760B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS523161A (en) | 1977-01-11 |
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