JPS6048909B2 - Active semiconductor device and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active semiconductor device and a method and method for manufacturing the same.

In particular, the present invention relates to an active semiconductor device that can operate at high speed by exploiting the difference in potential generated at a hetero-interface between semiconductor phases h having different electron affinities, and a method for manufacturing the same. Diodes are already known that are made by utilizing the difference in potential that occurs at the hetero-interface between semiconductors with different electron affinities, such as the hetero-interface between aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs). There is (BellLlbOratOriesRecOrd,
Sept, 198O, pp278). The principle is the first
As shown in Figures A and b, for example, gallium arsenide (GaA
s) Aluminum gallium arsenide (AlxGa
, -XAs) layer and gradually change its X value from one heterointerface to the other, and correspondingly, gradually change its electron affinity, the potential in thermal equilibrium state As shown in the figure, the distribution becomes sawtooth-like, forming a potential barrier and providing rectification. Potential diagrams when a forward voltage and a reverse voltage are respectively applied are shown in FIGS. 2A and 2B, respectively. SUMMARY OF THE INVENTION An object of the present invention is to provide an active semiconductor device capable of high-speed operation by utilizing the difference in potential generated at a hetero-interface between semiconductor layers having different electron affinities, and a method for manufacturing the same.

The gist of its structure is (a) For example, gallium arsenide (Ga
In contact with a layer (collector contact layer) made of a semiconductor with a high electron affinity such as As), for example, aluminum gallium arsenide (AlxGa, -XAs)
A layer (collector layer) made of a semiconductor with a small electron affinity is formed, and the value of the electron affinity of this collector layer is maximum at the part where it contacts the collector contact 3 layer, and when it is away from the collector contact layer. In this example, the aluminum (A1) content gradually increases so that the X value increases, for example, from 0 to 0. The temperature is increasing, and the contact with the collector layer is 40.
A layer made of a semiconductor with a high electron affinity, such as gallium arsenide (GaAs), which is extremely thin and has a thickness equal to or less than the free path of an electron, that is, a thickness of about 100 to 200 mm. (base layer) is formed, and a layer (emitter layer) made of a semiconductor with low electron affinity, such as aluminum gallium arsenide (AlxGa, -XAs), is formed in contact with the base layer. Therefore, the value of electron affinity of this emitter layer is minimum at the part where it contacts the base layer, and moreover,
This value is even smaller than the minimum value of the electron affinity of the collector layer, and as the value of electron affinity gradually increases with distance from the base layer, in this example, the content of aluminum (Al) gradually increases. The x value decreases from, for example, 0.3 to 0, and a layer (emitter contact layer) made of a semiconductor with a high electron affinity, such as gallium arsenide (GaAs), is in contact with the emitter layer.
It has a layered structure in which a collector electrode, a base electrode, and an emitter electrode are provided in the N collector contact layer, base layer, and emitter contact layer.

Indispensable matters for the structure of the present invention are (
b) There is a collector contact layer made of a semiconductor with a large value of electron affinity, and there is a collector layer in contact with this layer made of a semiconductor whose maximum value of electron affinity is not larger than the electron affinity of the collector contact layer. The electron affinity value of becomes gradually smaller as it moves away from the collector contact layer. /→There is a base layer that is in contact with this layer and is made of a semiconductor whose electron affinity value is not smaller than the minimum electron affinity value of the collector layer, and whose thickness is equal to or less than the free path of electrons. , (4) an emitter made of a semiconductor which is in contact with this layer and whose minimum value of electron affinity is even smaller than that of the collector contact layer, and whose value of electron affinity gradually increases as it moves away from the base layer. (There is an emitter contact layer made of a semiconductor whose electron affinity value is not smaller than the maximum value of the electron affinity of the emitter layer, which is in contact with the base layer.) , the emitter contact layer is provided with a collector electrode and a base electrode assembly emitter electrode, respectively.) The types of semiconductors that can be used include the above-mentioned aluminum gallium arsenide (AlxGal
-XAs) and GaAs, aluminum, gallium arsenide phosphorus (AlGaAsP), gallium phosphorus (GaAs), indium gallium arsenide phosphorus (InGaAsP) and indium phosphorus (InP),
There are many types, such as indium gallium antimony (InGaSb), indium gallium phosphorus (InP), gallium arsenide antimony (GaAsSb), and indium gallium antimony (InAs). The gist of the manufacturing method is as follows: (a) a semiconductor stack having the above layer structure is formed on a semi-insulating substrate using the molecular beam epitaxial growth method; and etch the surrounding area,
←→The collector electrode formation region of the above-mentioned semiconductor laminated J body remaining in this mesa shape is etched until it reaches the collector contact layer.

), etc., the insulating film in the base electrode formation region of the semiconductor stack is removed using the (holographic) method, and then the insulating film in this region is removed using the dry etching method. An opening reaching the base layer is formed in the semiconductor stack, and the insulating film in the emitter formation region of the semiconductor stack is removed using N phosphorography again.
Using molecular beam epitaxial growth method,
For example, gallium arsenide (GaA
A semiconductor layer having a large electron affinity as shown in s) is formed (for example, gallium arsenide (GaAs) formed in these regions, that is, the collector electrode formation region, the base formation region, and the emitter formation region). The purpose is to form a collector electrode, a base electrode, and an emitter electrode, respectively, on a semiconductor layer having a large electron affinity.
Of course, it is completely free to completely reverse the stacking order of the collector and emitter, and it goes without saying that a considerable degree of freedom is allowed in the types of semiconductors that can be used as described above. In addition, the etching end point can be determined by monitoring the emission wavelength (3967Λ) of aluminum (A1) plasma, which is a combination layer structure of a semiconductor containing aluminum (A1) and a semiconductor not containing aluminum (A1). A notable advantage is that it is possible to precisely control
? It is. Prior to describing the embodiments of the present invention, the operating principle P of the active semiconductor device according to the present invention will be explained with reference to the drawings.

FIG. 3a shows the distribution of potential with respect to layer thickness in thermal equilibrium state 1 of the semiconductor layer structure described above.

In the figure, CC represents a collector contact layer, C represents a collector layer, B represents a base layer, E represents an emitter layer, and EC represents an emitter collector layer. In this example, the potential difference P1 between the collector layer and the base layer is 0.2V, and the potential difference P2 between the emitter layer and the base layer is 0.
．． It is 3V. FIG. 3b shows the distribution of potential with respect to layer thickness in the above semiconductor layer structure when the base layer is grounded and a positive potential is applied to the emitter layer and a negative potential is applied to the collector layer. Here, the collector layer-base layer potential difference P1
, it is natural that the potential difference P2 between the emitter layer and the base layer remains unchanged. As mentioned above, the length of the base layer is equal to or less than the free path of electrons, and the potential difference P between the emitter layer and the base layer.

Since is larger than the potential difference P between the base layer and the collector layer,
The electron flow supplied from the emitter collector layer EC to the emitter layer E passes through the base layer B and reaches the collector layer C, if quantum mechanical reflection of electrons by the collector barrier is ignored. How much of the electron flow in the emitter layer E reaches the collector layer C is determined by the amount of energy that the electrons lose in the base layer B and the size of the collector layer barrier that must be overcome. be done. here,
If we assume that the loss electrons in the base layer B are 0 (zero) and the base current is 0 (zero), the power amplification factor A is the input impedance Rin and the output impedance Rou.
The ratio with respect to t is 0R0utA=--R1n, which means that it can function as an active semiconductor device having an amplification function.

In addition, this does not lose energy in base layer B! The electrons that could not exceed the 5ta barrier have a base current I
B, but the common emitter current amplification factor β is the base current I
Naturally, the ratio to the B collector current Ic is ICβM 4O.

Here, it is worth noting that since the base current IB can be made extremely small by selecting the layer structure, it is not difficult to make the current amplification factor β extremely large. Therefore, the active semiconductor device according to the present invention is functionally an N-P-N type bipolar transistor.

It is considered to be a similar active semiconductor device, and the circuit is ιN-P.
- It can be used in the same way as an N-type bipolar transistor, but the difference from the N-P-N type bipolar transistor is that it uses no PN junction, does not use holes, and has high mobility. Since only the high electron b is used, high-speed performance is extremely low. Embodiment I of the present invention (each of the main steps for manufacturing such an active semiconductor device) will be explained in detail below with reference to the drawings to further clarify the structure and unique effects of the present invention.

Referring to FIG. 4, a semiconductor stack having the crystal parameters shown below is formed on a substrate made of non-doped semi-insulating gallium arsenide (GaAs) using a molecular beam epitaxial growth method.

N-type impurity layer name Material Thickness concentration 8 CTn-3 Collector GaAs5, OOO2 x 1018 Contact layer Collector layer AI x Gal- Increase below) Add base layer GaAslOO2×1018 Emitter layer AIxGa, -XAs2OO〃1018 However, X decreases from 0.3 to 0 from the bottom toward the soil degree is desirable.

In order to change the X value of the collector layer and the emitter layer, it is effective to change the amount of evaporation of aluminum (A1) by controlling the temperature of the aluminum (Al) open. Silicon (Si) is suitable as a dopant. In this embodiment, the collector layer is an undoped layer, because in the operating state of this active semiconductor device, a large reverse voltage is applied to the collector layer. This is to increase the breakdown voltage. Therefore, when the magnitude of the reverse voltage applied to the collector layer is relatively small, there is no point in making it undoped, and it is rather preferable that it be doped to an N-type like the other layers. Therefore, this doping state does not define the gist of the invention. In the figure, in JO, 1 is semi-insulating gallium arsenide (Ga
2 is a collector contact layer made of a gallium arsenide (GaAs) layer, and 3 is an undoped aluminum gallium arsenide (GaAs) substrate whose X value increases from o to 0.2 from bottom to top. AlxGal-5xA
s) layer, 4 is a base layer made of an N-type doped gallium arsenide (GaAs) layer, and 5 is an X value that decreases from 0.3 to o from the bottom to the top. N-type aluminum gallium arsenide (Alx
6 is an emitter layer made of an N-type gallium arsenide (GaAs) layer. Referring to FIG. 5, a mask is formed on the element formation region using a phosphorography method, and the semiconductor stack is mesa-etched using a hydrofluoric acid (etching solution) so as to leave the element formation region; Next, using the phosphorography method again, a mask is formed on the area excluding the collector electrode forming area, and using a hydrofluoric acid etching solution, a part of the collector layer 2 is left on the collector electrode forming area 7. to remove the semiconductor stack.

See FIG. 6. The substrate surface was grown using chemical vapor deposition using silicon dioxide (SiO).

) layer 8, an opening is formed in the silicon dioxide (SiO2) layer 8 in the base electrode formation region 9 using a hydrofluoric acid (HF) based etching solution using a phosphorography method, and Emitter contact layer 6, emitter layer 5 and part of base layer 4 are removed using a reactive plasma etching method with carbon fluoride (CCI.F2) as the reactive material. At this time, the thickness of the base layer 4 is only 1
00Λ, the etching must be stopped as soon as it reaches the base layer 4. In order to make this possible, it is effective to utilize light emission from aluminum (A1) plasma. That is, the etching process is stopped immediately after the emission wavelength of 3.960 Λ of aluminum (A1) plasma is monitored using a sensor such as a photodiode and the emission of light is stopped. It has been experimentally confirmed that this monitoring method makes it possible to stop etching within the base layer 4 with an accuracy of ±20 to 30Λ. Refer to Fig. 7 Hydrofluoric acid (HF)-based processing using phosphorography method 1. Silicon dioxide (Si
O.

) An opening is formed in the layer 8, and a base electrode formation region 9, an emitter electrode formation region 10, and a collector electrode are formed using the molecular beam epitaxial growth method using the silicon dioxide (SiO2) layer 8 as a mask. Area 11 and 10
A gallium arsenide (GaAs) layer 12 doped to be N-type at a high concentration of approximately 100.degree./d is formed.

Here, a monocrystalline gallium arsenide (GaAs) layer is formed on each electrode forming region 9, 10, 11, but amorphous gallium arsenide (GaAs) layer is formed on the silicon dioxide (SiO.) layer 8 used as a mask. (GaAs) layer is formed. A plasma etching method with carbon dichloride difluoride (CCI.F.) as the reactive agent is used to completely etch the substrate. When etching a surface, the etching rate of amorphous gallium arsenide (GaAs) is about twice that of single crystal gallium arsenide (GaAs), so silicon dioxide (SIO).

) The amorphous gallium arsenide (GaAs) layer on layer 8 is removed, but the single crystal gallium arsenide (GaAs) layer on each electrode formation region 9, 10, 11 remains.

Refer to FIG. 8. Here, a single crystal gallium arsenide (GaAs) layer 12 deposited in the emitter electrode formation region 10 and a single crystal gallium arsenide (GaAs) layer deposited in the beta electrode formation region 9 are used.
) layer 12 through the emitter contact layer 6; It is clear from the N-type impurity concentration (2 x 10"/d) and layer thickness (4808) that the region indicated by diagonal lines 13 in the figure is almost depleted due to the surface depletion layer. , the electrode formation regions 9 and 10 will not be short-circuited.

Refer to Figure 9. Finally, place gold/germanium/gold (AuGe/gold) on the substrate.
After vacuum-depositing the Au) layer, each electrode forming area 9, 10,
This is removed from areas other than 11 to complete the gate electrode 14, emitter electrode 15, and collector electrode 16, thereby completing an active semiconductor device according to an embodiment of the present invention.

Refer to FIG. 10. The potential distribution in the thermal equilibrium state of the layer structure of the active semiconductor device according to this embodiment is approximately as shown in FIG.

See FIG. 11 However, since the essence of the present invention has already been described above, the state of change in electron affinity in the emitter layer and collector layer is not limited to that shown in FIG. 3b or FIG. 10. , including those shown in Figures 11A and b,
There can be many different things.

Furthermore, the minimum value of the electron affinity between the collector layer and the emitter layer can also be freely selected according to the desired characteristics.

As explained above, according to the present invention, functionally N-P
-Similar to N-type bipolar transistor, but P-N
It is an active method capable of high-speed operation that does not use any junctions or utilizes the electron flow that moves with high mobility due to the difference in potential that occurs at the hetero-interface between semiconductors with different electron affinities. It is possible to provide a semiconductor device and a method for manufacturing the same.

Types of semiconductors that can be used in the present invention include combinations of aluminum gallium arsenide (GAlxGal-XAs) and potassium arsenide (GaAs), as well as the following combinations.

Ding

[Brief explanation of the drawing]

FIGS. 1A and 1B and FIG. 2 are auxiliary diagrams for explaining the principle of a diode that utilizes the difference in potential generated at the hetero-interface between semiconductors having different electron affinities. FIGS. 3A and 3B are auxiliary diagrams for explaining the operational functions of the active semiconductor device according to the present invention. 4, 5, 6, and 7 are cross-sectional views of a substrate showing each main step of a method for manufacturing an active semiconductor device according to an embodiment of the present invention. FIG. 8 is an auxiliary diagram illustrating that the base region and the emitter region are separated and insulated by the surface depletion layer. FIG. 9 is a cross-sectional view of a substrate showing a completed state of an active semiconductor device according to an embodiment of the present invention. FIG. 10 shows a potential distribution diaphragm in a state of thermal equilibrium between the layers of the active semiconductor device shown in FIG. 9. FIG. 11 is a potential distribution diaphragm in a state of thermal equilibrium between layers of an active semiconductor device according to another embodiment of the present invention. 1...
...Substrate (semi-insulating gallium arsenide substrate), 2...
...Collector contact layer (gallium arsenide layer),
3... Collector layer (undoped aluminum gallium arsenide layer with varying X value), 4... ・
...Base layer (N-doped gallium arsenide layer), 5
...Emitter layer (N-doped aluminum gallium arsenide layer with varying X value), 6 ...
Emitter contact layer (N-gallium arsenide layer), 7.
... Collector electrode formation region, 8 ... Silicon dioxide layer, 9 ... Base electrode formation region,
10...Emitter electrode formation region, 11...
... Collector electrode formation region, 12 ... Highly N-doped gallium arsenide layer, 13 ... Depleted region, 14 ... Gate electrode, 15 ...・
...Emitter electrode, 16...Collector electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor layer (collector contact layer) having a large electron affinity, which is formed in contact with the collector contact layer, and whose maximum value of electron affinity is equal to or less than the electron affinity of the collector contact layer. A layer (collector layer) made of a semiconductor having a composition distribution in which the value of electron affinity decreases as the distance from the collector contact layer increases, and a layer formed in contact with the collector layer and having a thickness equal to or less than the free path of electrons. a layer (base layer) made of a semiconductor having an electron affinity larger than the minimum electron affinity of the collector layer, and a layer formed in contact with the base layer and having a minimum electron affinity of the collector layer A layer (emitter layer) made of a semiconductor having a composition distribution such that the value of electron affinity increases with distance from the base layer, which is smaller than a minimum value, and a semiconductor layer formed in contact with the emitter layer and having a large electron affinity. (emitter contact layer), and the collector contact layer, the base layer, and the emitter contact layer each have a collector electrode, a base electrode, and an emitter electrode. 2 (a) Using the molecular beam epitaxial growth method, a semiconductor layer (collector contact layer) having a large electron affinity is formed on a semi-insulating substrate, and a semiconductor layer (collector contact layer) having a maximum electron affinity is formed on a semi-insulating substrate. A semiconductor layer (collector layer) having a composition distribution that is equal to or less than the electron affinity and whose electron affinity value decreases as the distance from the collector contact layer increases, and a thickness equal to or less than the free path of electrons. a layer (base layer) made of a semiconductor having an electron affinity larger than the minimum value of the electron affinity of the collector layer; Forming a laminate consisting of a semiconductor (emitter layer) having a composition distribution such that the electron affinity value increases, and a semiconductor layer (emitter contact layer) having a large electron affinity; (b) forming the laminate; (c) removing the laminate until reaching the substrate, leaving a desired area of
removing a desired region of the remaining stacked layer until reaching the collector contact layer; (d) forming a layer made of an insulator on the surface of the stacked body from which the partial region has been removed; e) forming an opening reaching the base layer in a desired region of the laminate using a phosphorography method, and (f) forming an opening reaching the base layer in a desired region of the laminate using a phosphorography method; (g) using a molecular beam epitaxial growth method, the stack was removed until the collector contact layer was reached; forming a semiconductor layer having a large electron affinity in the region, an opening reaching the base layer, and the emitter electrode formation region;
h) forming a collector electrode, a base electrode, and an emitter electrode on the semiconductor layer having a large electron affinity formed on the collector contact layer, the opening reaching the base layer, and the emitter electrode formation region; A method for manufacturing active semiconductor devices.