JPS6048934B2 - semiconductor level amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor level amplification circuit that can amplify an input level with little power consumption in a semiconductor device.

As shown in FIG. 1, conventional semiconductor level amplifier circuits invert the input level with an inverter circuit 1, and then obtain an output through a level amplification inverter circuit (2) which amplifies and inverts the input level.

When such an input level amplifier circuit is used in a semiconductor device using a P-channel MOS transistor or an N-channel MOS transistor, the input level ``H'',
``L'' causes a state in which a current flows in either the inverter circuit I or the level amplifying inverter circuit (2) in a direct current manner. When a circuit like the one shown in FIG. 1 is used in an input level amplification section of a semiconductor device or the like, the above-mentioned direct current may account for a considerable proportion of the power consumption of the semiconductor element.

FIG. 2 is a circuit diagram showing an actual example of a MOS and an IC based on the conventional circuit configuration method shown in FIG.

That is, transistor Ti and transistor T. is the first
The transistor T corresponds to the inverter circuit I in the figure. ,
T. , T, and capacity Hρ correspond to the level amplification inverter circuit (2). Note that VDD and VSS are a ``H'' power source and a ``L'' power source. Figure 2 is N channel M
The operation of this circuit will be explained assuming that it is composed of OS transistors. When the F input is ``L'', the L transistor T is in a non-conducting state (hereinafter referred to as QFF), and the load transistor T2 causes the output of the P point corresponding to the output point of the inverter circuit I in FIG. The level becomes "'H". This “H” level is the gate 5 of transistor T3.
The transistor Ta is in a conductive state (
(hereinafter referred to as ON). Therefore, the output becomes ``L'' level due to the ratio of transistors T3 and T4.
At this time, a direct current flows through transistors T3 and T4. Therefore, when a circuit as shown in Fig. 2 is used as a clock input level amplification circuit of a semiconductor device using an N-channel MOS transistor, the clock input becomes ``L''.
'' (when the semiconductor element is in standby state),
The input level amplifier circuit is constantly consuming power. However, it is preferable that the semiconductor element consumes zero power in a standby state.

The same can be said of semiconductor elements using P-channel MOS transistors. However, conventional level amplifier circuits have the disadvantage that they always consume power even in standby mode. The present invention has been made in view of the above points, and is intended to provide a level amplification circuit that consumes only 0 power in a standby state.

This invention will be explained below. FIG. 3 shows an embodiment of the present invention.

The structure and operation of this embodiment will also be explained assuming that N-channel MOS transistors are used. In FIG. 3, 10 to 17 are transistors, 18 is a capacitor, and 1
9 to 24 are terminals, 25 is a load capacitance of the transistor 11, and 26 is a gate of the transistor 15.

Now, the input is connected to the gates of transistors 11 and 14, and further connected to the gate capacitor 18 of transistor 16 through transistor 15 as a switching element.
Transistor 10 is a load transistor for transistor 11.
“A resistor may be used to act as a resistor. Since transistors 10 and 11 are a circuit for creating a signal that is an inversion of the input, a bootstrap circuit may be used.
The drain of the transistor 14 is connected to the source of the transistor 18, and the source of the transistor 14 is grounded. The gate of transistor 13 is connected to the output of the circuit for inverting the input signal. transistor 1
The drain of 8 is connected to the source of transistor 12,
Furthermore, it is also connected to the capacitor 18. 4 Since transistor 12 acts as a load transistor for transistors 13 and 14, a resistor may be used instead.

Alternatively, a bootstrap configuration as shown in FIG. 5 may be used. That is, transistors 30 and 31 in FIG.
and capacitor 32 have a function corresponding to transistor 12, and transistors 13 and 14 are the same as those shown in FIG. The source of transistor 17 is grounded, and the gate is connected to the gate of transistor 13.

The drain of the transistor 17 is connected to the source of the transistor 16, and the gate of the transistor 16 is connected to the drain of the transistor 15 and also to one terminal 21 of the capacitor 18. The drain of transistor 16 is connected to the power supply. The gate 26 of the transistor 15 is normally set to the ``H'' level by human power.
It is desirable to set the potential near the value obtained by adding the threshold voltage of . 7.If the input ``H'' level is VIH) the threshold value of the transistor 15 is Vth) and the potential of the gate 26 is VC26, then Vth<VC26<VIH+Vt
h.

In this case, the gate 26 may be connected to the gate of the transistor 13, that is, the terminal 19, as shown by the dotted line.

Note that the transistors 16 and 17 are circuits for increasing the fan-out of the level amplification circuit of the present invention, and are not the main part of the present invention.

Now, in FIG. 3, when the input is ``L'' (standby state), transistors 11 and 14 are OFF.

The transistor 15 at the terminal 21 is in the ON state, and the terminal 21 has the same "L" level as the input. At this time, no current flows between the power supply VDD and ground. Power consumption in standby mode is 0. The terminals 19 and 22 are charged to the "H" level by the load transistors 10 and 12, respectively. This state corresponds to period A in the operating waveform diagram of FIG. Next, when the input becomes ``H'', terminal 21
is almost the same ``H'' as the input through transistor 15.
become the level.

At this time, transistors 11 and 14 are also turned ON. When the transistor 11 turns ON, the terminal 19 becomes ``L'', turning the transistor 13 OFF. At this time, transistor 1
The 0FF of transistor 3 occurs with a certain time delay from the 0N of transistor 14. The time delay is determined by the ON resistance value of the transistor 11 and the value of the load capacitance 25. Due to this time delay, the terminal 22 becomes ``L'' level due to the ratio of transistors 12, 13, and 14, and transistor 13 becomes 0.
After becoming FF, it returns to 'H' level again. This is period B in FIG. When the terminal 22 is at the ``L'' level, the terminal B2l is charged to almost the same level as the input ``H'' level, so the terminal 22 is at the ``L'' level.
When the “H” level returns, the terminal 21 is
The ``H'' level is a sufficiently large ``H'' level.

At this time, the transistor 15 is apparently in the 0FF state. It is well known that the ``H'' level of the input terminal becomes the source for the gate 26 of the transistor 15, and the threshold value of the transistor 15 becomes apparently large, resulting in an 0FF state. Therefore, a sufficient "H" level at the terminal 21 can be maintained. Note that the transistor 15
If the gate 26 and the terminal 19 are connected as shown by the dotted line, the transistor 15 becomes OFF at the same time as the transistor 13 becomes OFF. Therefore, the terminal 21 can maintain a sufficient "H" level. This is period C in FIG. Next, when the input becomes ``L'' level, transistors 11 and 14 become 0FF, and transistor 1
5 becomes 0N.

Therefore, the terminal 21 becomes "L" level.Terminal 1
9 is charged to ``H'' level by transistor 10, and transistor 13 is turned ON. The terminal 22 holds the H level because the transistor 14 is OFF. This corresponds to period D in FIG. 4, which is the same state as period A. Although the N-channel MOS transistor process has been described above, the same explanation can be applied to cases where other processes are used. FIG. 6 shows the basic circuit of this invention.

In this code, I is an inverter circuit, ■ is a level amplification inverter circuit, and the level amplification inverter circuit (j) includes driver elements ■A, ■B, load element ■C, and capacitor ■D that amplifies the output level. , a switch element (E) that electrically opens and closes the input and output, and a control element (F).The terminals 1920, 21, and 22 are shown in correspondence with FIG. The embodiment shown in FIG. 3 can basically be expressed as θ in FIG. Note that in the basic circuit shown in FIG. Alternatively, as shown in FIG. 7, the input signal may be passed through another inverter circuit I', and its output may be connected to the control terminal ■F. In this invention, when the input is at the ``L'' level and immediately after the input goes to the ``H'' level, the switch element ■E is in a conductive state, and the input is ``''
When the level becomes H'', driver element ■A becomes conductive.
Driver element ■B becomes non-conductive, and terminal 22 becomes '
It is sufficient that the switch element ΠE becomes substantially non-conductive when the level changes from the 'L' level to the 'H' level.

Figure 8 shows an example of a circuit actually used.
This example deals with the case where the clock input of a device made using a channel MOS process is input at TTL level, but it can also be applied to devices made using other processes.

In FIG. 8, VDD is a power supply for the MOS semiconductor device, and Vcc is another power supply for allowing the input and output of the MOS semiconductor device to be directly connected to ΠL. This circuit uses two stages of circuits according to the present invention in order to sufficiently bring out the output level of the level amplifier circuit up to the power supply voltage.
A transistor TA is connected to the inverter circuit of the second stage level amplifier circuit so that the threshold value of the transistor TB becomes larger with respect to the input signal. Further, transistors Tc and TD are connected to increase the fan-out of the output. As described above in detail, the present invention comprises both an inverter circuit and a level amplifying inverter circuit using MOS transistors, and both circuits are in an inactive state with zero power consumption in a standby state. Since both circuits operate and perform the required action only when the input is applied, there is no power consumption in the standby state, and the advantage is that the intended purpose can be fully achieved. .

[Brief explanation of drawings]

1 and 2 are block diagrams and circuit diagrams showing an example of a conventional level amplifying circuit 40, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is a diagram showing another circuit example of the main part in FIG. 3, FIG. 6 is a basic circuit diagram of this invention, and FIG. 7 is a diagram showing another embodiment of this invention. The diagram shown in FIG. 8 is an example of an actual circuit using the present invention. In the figure, 10 to 17 are transistors, 18 are capacitors, and 19 to 17 are transistors, 18 are capacitors, and 19 to 17 are transistors.
24 is a terminal, 25 is a load capacitor, and 26 is a gate.

Claims (1)

[Claims] 1 An inverter circuit using a MOS transistor that is in an inactive state with zero power consumption in the standby state and is activated by the application of input from the input terminal to invert the input level, a load element, a first MOS transistor, and a second MOS transistor. MOS transistors are connected in series, and the output of the inverter circuit is applied to the gate of the first MOS transistor, and the input of the inverter circuit is applied to the gate of the second MOS transistor. a circuit, a capacitive element having one end connected to a connection point between the load element of the restoration circuit and the first MOS transistor directly connected to the load element, and the other end of the capacitive element and the inverter. connected between the input end of the circuit,
a third MO for charging the capacitive element when the potential at the connection point of the recovery circuit temporarily decreases and then increases;
A semiconductor level amplifier circuit comprising an S transistor, and an output is taken out from the other end of the capacitive element.