JPS6048995B2 - Abnormality detection circuit for thyristor conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection circuit for a thyristor conversion circuit that detects an abnormality in each arm of the thyristor conversion circuit as well as an abnormality in the thyristor conversion circuit itself.

Conventionally, there has been no suitable circuit for detecting abnormalities in thyristor conversion circuits. For this reason, it was inevitable that the damage would be greater in the event of an accident. These accidents include the following: (1) In the case of breakover a The energization period of the arm that has broken over becomes longer,
The rating of the anode reactor used to protect the thyristor used in this arm was exceeded and it burned out.

If the Jb arm is made up of a plurality of thyristors connected in parallel, current will concentrate on the element that has broken over, accelerating the state a mentioned above.

For this reason, for example, the fuse blows and the external state returns to normal, but the remaining thyristors exceed their ratings and eventually break, increasing the damage caused by the accident. When the c-arm is in breakover, phase control becomes impossible when speed is reduced.

As described above, in the case of a breakover, an abnormality cannot generally be detected unless all of a certain arm becomes abnormal.

For this reason, not only did the damage caused by the accident increase, but it also took time to recover, which caused problems in terms of improving the operating rate. The following describes accidents other than breakovers.

(2) In the case of anti-parallel short circuit In both forward and reverse thyristor conversion circuits, when the thyristor for one phase of the forward conversion circuit is conducting, the forward current is applied to the thyristor in the reverse conversion circuit. When an error pulse due to noise or the like is applied to the gate, an anti-parallel short circuit occurs between the forward-reverse thyristor conversion circuits.

Conventionally, for this detection, a current detection circuit is provided for each of the forward and reverse directions, and an anti-parallel short circuit is detected by determining that the difference between the two is greater than a certain value. (3) Commutation failure If there is re-acceleration during regenerative braking, commutation failure is likely to occur, but it can be said that there is no conventional detection method for this.
Wait until commutation failure occurs and excessive current occurs, and then shut off the circuit with a fuse or circuit breaker! was blocking it.

For this reason, when the circuit is cut off, it is impossible to operate it unless a fairly large current flows, and the damage caused by an accident is generally great. As described above, the three effective measures for thyristor conversion circuits have not been taken in the past.

The present invention has been made in view of the above-mentioned conventional drawbacks, and is an abnormality detection method for a thyristor conversion circuit 4 that can quickly detect an abnormality in a thyristor element by detecting a change in the current conduction period of the thyristor element. The purpose is to provide circuits. The present invention focuses on the fact that the conduction angle of the line current of each phase of the AC power supply in a thyristor conversion circuit is different between normal and abnormal conditions, and changes in this conduction angle are determined by the gate pulses of the own phase and other phases. By using and detecting this, it is possible to detect an abnormality in a thyristor connected to a thyristor conversion circuit.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Three-phase bridge connected thyristors 1, 2, 3, 4, 5
, 6 are connected to a three-phase AC power source 7 on their AC input sides, and a load 8 is connected to their DC output sides.

A gate pulse generator is connected to each of the thyristors 1 to 6, and ignition is performed sequentially for each phase in a predetermined phase.
Current transformers 10U and 10■ are installed in each phase of U, ■, and W of AC power supply 7.
, 10W1 are provided to detect the current value and send it to the abnormality detection circuit 100 as the current flow angle of each phase. The abnormality detection circuit 100 detects the ignition pulse and voltage for each phase. The presence or absence of an abnormality in the thyristor is detected based on the flow angle, and based on this detection, a circuit breaker or the like is operated to stop the power supply to the thyristor converter.

FIG. 2 shows the firing pulses and current flow angles of each phase when the thyristor conversion circuit is in normal operation.

Fig. 2A is a diagram showing the line voltage waveform of the AC power supply 7, Fig. 2B is a diagram showing the gate pulse signal of each phase (when the control delay angle α=30), and Fig. 2C is a diagram showing each phase. It is a figure showing the line current (current conduction angle) flowing through. When all of the thyristors 1 to 6 are normal, the line currents flowing through the U, ■, and W phases have a phase difference of 1200 on both the positive side and the negative side, and each phase is in a balanced state. Here, only Up will be considered as an example.

When thyristor 1 is normal, the period of current flowing through the U phase is the gate pulse signal (main pulse) of the U phase.
There is only a period of 120 from when MP1 occurs as shown in FIG. 2B until the Vp phase gate pulse signal MP2 is generated (in this case, the current overlap angle is not considered).
.

Note that the relationship between this gate pulse signal and the current flow period does not change even when the gate pulse signal is phase-shifted (when α changes). Conversely, if the Up phase thyristor 1 is abnormal (however, in this case, open failure is not considered)
, since current always flows outside of the above-mentioned conduction period, V
During the period from when the two-phase gate pulse MP2 is output to when the Up-phase gate pulse MP3 is output, the Up-phase current (Fig. 2B
By detecting whether or not the period (X period shown in the figure) flows, it is possible to determine whether or not the thyristor 1 is normal.

FIG. 3 is a circuit diagram showing in detail the abnormality detection circuit of the present invention.

Although Fig. 3 only shows the Up phase among the three phases, the other phases can also be configured with the same circuit, U, ■, W.
The abnormality detection circuit is configured for three phases.

4A, B, C, D, E, F, G, and H are operation waveform diagrams of each part of the circuit shown in FIG. 3, respectively.

The operation will be explained in detail based on FIGS. 3 and 4.

Gate pulse generator 9 generates gate pulse pair 2 as shown in FIG. 4A.
1 (corresponding to the self-phase pulse) is generated, and then, as shown in FIG. 4B, a gate pulse MP2 (a pulse of a phase delayed by 1200) is generated.

When this gate pulse MP2 is generated, the delay circuit 101 (
For example, a pulse signal with a predetermined delay time Td- is obtained using a monostable multivibrator. The reason for providing such a delay time is to prevent the abnormality detection circuit from malfunctioning due to the current overlap angle. The pulse signal obtained by the delay circuit 101 is input to the memory circuit 102 (flip-flop), and at a certain time, the output signal thereof becomes high level, resulting in a reset state.

This output signal is input to the next-stage AND circuit 103, but during normal operation, only the output signal of the memory circuit 102 is applied, so the AND circuit 103 does not operate, and the subsequent circuits are in an inoperable state. The memory circuit 102 is reset at time T2 as shown in FIG. 4C by the Up-phase self-phase gate pulse M. This gate pulse M is input from the gate pulse generator 9 to the reset terminal of the memory circuit 102 via the OR circuit 104. (In addition, OR circuit 1
The other input terminal of 04 is configured so that an external reset signal can be applied thereto. ) The case where all the thyristor conversion circuits are normal has been described above, but next, the case where there is an abnormality in the U phase will be explained.

Under normal conditions, the Up phase current is flowing as shown in Figure 4D, but if there is an abnormality (breakover) in thyristor 1, the current is already flowing at a certain stage as shown in Figure 4E. It starts to flow. At this time, the U-phase current is detected by the current transformer 10U (detected at all times, including during normal operation), and is input to the comparator 106 after removing harmonics and the like through the filter 105.

A bias circuit 107 is placed at the input of the comparator 106, and adjusts the current detection level D by the current transformer 10U to an arbitrary value to prevent malfunctions due to noise etc. (as shown in Figure 4E) ). FIG. 4F shows the output signal waveform of the comparator 106. Under this condition, as described above, the memory circuit 102 operates as the fourth gate pulse based on the gate pulses of each phase.
It is in the set state as shown in Figure C.

Therefore, the comparator 106 becomes high level at time T2.
The output signal is input to the AND circuit 103 at the same time as the output signal of the memory circuit 102. As a result, an output signal having a width between time T2 and time T2 as shown in FIG. 4G is obtained. The output signal of the AND circuit 103 is input to the set terminal of the memory circuit 108 (flip-flop), and the output signal becomes high level as shown in FIG. 4H. This high level state is maintained unless a reset signal is input to the terminal 109. An alarm circuit 110 operates based on a signal from the memory circuit 108, and provides an alarm by an alarm sound or a lamp display.

In this case, if the output signal of the memory circuit 108 is used as is, the alarm will be issued continuously and will continue until it is reset. This reset is provided for reset at the time of recovery from abnormality and for initial reset. Note that the output signal of the memory circuit 108 is simultaneously transmitted to other control devices, such as
It is also used as a control signal to operate a circuit breaker or the like to cut off a thyristor conversion circuit. The above is an explanation of the operation when the Up phase thyristor 1 breaks over), but other abnormalities such as detection of breakdown of the thyristor element, anti-parallel connection due to malfunction such as noise in the anti-parallel conversion circuit, It can also be applied in the case of commutation failure during inverter operation (during deceleration operation).

An explanation of these points will be added based on the drawings. FIG. 5 is an explanatory diagram showing a current path when an anti-parallel short circuit occurs in an anti-parallel conversion circuit.

In this embodiment, a three-phase bridge rectifier for reverse rotation is added to the embodiment shown in FIG.

The reverse bridge rectifier consists of thyristors 7, 8, 9, 10,
11 and 12, and are connected in opposite polarity to the normal rotation bridge rectifiers 1 to 6. In this case, a DC motor 13 is used as the load. Although the entire abnormality detection circuit is not shown in FIG. 5, it is the same as that shown in FIG. 3. In FIG. 5, for example, if current is flowing between thyristor 1 and thyristor 4 as shown by the dotted line between phases U to
is fired, the current from the U phase flows through thyristors 1 and 11.
, W phase is short-circuited in the normal path.

However, even in this case, the abnormality detection circuit 100 can detect this short circuit abnormality. Abnormality detection circuit 100
The operations, effects, etc. are all the same as shown in FIG. FIG. 6 is an explanatory diagram showing the current path during inverter operation.

In this embodiment, a bridge rectifier is configured with thyristors 14, 15, 16, 17, 18, and 19 so that the polarity is reversed when viewed from the power source 7 side, and a regenerative operation is performed using DC and an electric motor 13 as a load. It shows.

During regenerative operation, the thyristors 14 and 17 are fired, and the electric power of the motor 13 is transferred to the power supply 7 side, and regeneration is performed, for example, along the route indicated by the dotted line in FIG. Even if there is a commutation failure (for example, in thyristor 19) and other thyristors are fired, the abnormality detection circuit 100 operates and can detect the abnormality.

(In Fig. 6, the gate pulse generator 9, the abnormality detection circuit 10
In both cases, only one phase j is shown. ) In this embodiment, the operation, effects, etc. of the abnormality detection circuit 100 are all the same as in the embodiment shown in FIG. Furthermore, abnormality detection circuit 1
By making variable the delay time Td of the delay circuit 101 of 00 and the voltage detection value 6 by the bias circuit 107, various detection delay times and detection levels can be set.

As is clear from the above, according to the present invention, an abnormality can be determined by detecting the instantaneous value of the current, so it is possible to detect an abnormality at an extremely high speed, and it is also possible to take countermeasures such as cutting off the circuit before secondary destruction occurs. .

In the embodiments of the present invention, a case where the present invention is applied to a three-phase AC power source is dealt with, but the present invention is not limited to this, and can be applied not only to a polyphase circuit having three or more phases but also to a two-phase AC power source.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 A, B,
Each of C is an operation waveform diagram of each part of the embodiment shown in FIG.
Fig. 3 is a detailed circuit diagram of an embodiment of the present invention, Fig. 4 A, B,
C, D, E, F, G, and H are operating waveform diagrams of each part of the embodiment shown in Figure 3, and Figure 5 shows the current path when an anti-parallel short circuit occurs in the anti-parallel conversion circuit. The explanatory diagram, FIG. 6, is an explanatory diagram showing the current path during inverter operation. Explanation of symbols: 1, 2, 3, 4, 5, 6...Thyristor, 9...Gate pulse generator, 10U, 1
0■, 10W...Current transformer, 100...
Abnormality detection circuit, 101...Delay circuit, 102.
... Memory circuit, 103 ... AND circuit, 105 ... Filter, 106 ... Comparator,
107...Bias circuit, 108...
Memory circuit, 110...Alarm circuit.

Claims (1)

[Scope of Claims] 1. An abnormality detection circuit for a thyristor conversion circuit that detects an abnormality in the thyristor in a thyristor conversion circuit that includes a thyristor controlled by a firing pulse and performs forward conversion or inverse conversion. A memory that uses as a reset signal a firing pulse to a thyristor that conducts electricity in one phase of an AC power supply of a circuit, and uses a firing pulse as a set signal to a thyristor that conducts electricity in another phase that is delayed in phase by 120 degrees from the above-mentioned one phase. a current transformer that detects the current flowing in the one phase of the thyristor conversion circuit; and an AND circuit that uses the detection signal obtained by the current transformer and the output signal of the memory circuit as input signals to generate an output signal. , means for displaying an alarm of an abnormality in the thyristor conversion circuit based on the output signal of the AND circuit. 2. An abnormality detection circuit for a thyristor conversion circuit according to claim 1, further comprising a delay circuit that provides a predetermined delay time to a set input signal in order to prevent malfunction of the memory circuit. 3. A filter that removes unnecessary signals from the detection signal of the current transformer, a comparator that sends an output signal to the AND circuit only when the output signal of the filter exceeds the set value, and a An abnormality detection circuit for a thyristor conversion circuit according to claim 1, further comprising: a bias circuit for setting .