JPS6049328B2 - Decimal quadruple generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary quadruple generation circuit for generating a binary quadruple number (binary w displacement).

One way to generate a quadruple of a binary decimal number is to add the binary w expulsion four times using a w-ary arithmetic unit, but this requires a long calculation time and is suitable for fields that require high speed. It cannot be used.

Therefore, conventionally, the Kawashin quadruple generation circuit shown in FIG. 1 has been widely used.

To briefly explain this circuit, the binary m-exclusion to be multiplied by 4 (input binary m-exclusion) is shifted by 2 bits toward the higher digits by the shift circuit 4 and becomes one input of the binary arithmetic unit 1. .

In addition, in input binary code elimination, each digit is encoded by the encoding circuit 2 according to the encoding rule shown in FIG. It later becomes the other input of the binary arithmetic unit 1. Binary operator 1
adds the two inputs in binary, and the input binary evolution w expulsion is 4
Outputs the doubled binary evolution Ru expulsion.

By the way, the above-mentioned conventional Kawashin quadruple generation circuit has the following problems. That is, the encoding circuit 2 cannot encode each digit of the input binary m-exclusion independently, but must refer to the lower digits. Specifically, as shown in FIG. 2, the output sign for the input digits (0010)O and (0111)2 changes depending on the value of the fifth digit below it.

This is an obstacle to increasing the speed of the encoding circuit 3. Further, the encoding circuit 2 is often configured into logical blocks in units of digits or bytes, but in this case, communication between each logical block is required, which poses a problem in implementing the logical blocks. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a w-adic quadruple generation circuit that solves the above-mentioned problems.

Another object of the present invention is to provide a 1-attack-4-multiplier generation circuit that can effectively utilize 6 addition circuits and 6 subtraction circuits in the w-ary arithmetic circuit included in a processing device capable of w-ary arithmetic processing. .

The main features of the w-adic quadruple generation circuit according to the present invention are that it includes an encoding circuit that encodes each digit of an input binary w-adic number regardless of the lower digits, and a binary arithmetic unit that performs binary addition. The point is that six adder circuits are provided on the input side of the circuit, and a subtracter circuit is provided on the output side.

Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 3 is a block diagram of a w-adic quadruple generation circuit according to the present invention. The input binary coded 1 pheasant number for which a quadruple is to be calculated is shifted by 2 bits to the left (upper row digit side) by the shift circuit 4, and is input to one of the inputs of the binary arithmetic unit 1 in the w-ary arithmetic circuit 7. Become.

In addition, the input binary W-adic number is encoded by the encoding circuit 8, and further shifted by 1 bit to the left (higher digit side) by the shift circuit 3. 6 adder circuit 5. The output of this 6-adder circuit 5 becomes the other input of the binary arithmetic unit 1. The binary arithmetic unit 1 performs binary addition of the two inputs, and inputs the result to a 6-subtraction circuit 6 for correcting w-adic calculations.

The output of this 6-subtraction circuit 6 is the quadruple number (binary W-adic number) that is to be obtained. The correspondence between the input and output of the encoding circuit 8 is shown in Figure 4a. That's right.

As is clear from the figure, the encoding circuit 8 encodes each digit of the input binary W-adic number regardless of other digits. The correspondence between the input and output of the 6-addition circuit 5 is as shown in FIG. 4b, and the correspondence between the input and output of the 6-subtraction circuit 6 is as shown in FIG. 4c.

Next, the operation will be described using as an example a case where an input binary coded w-adic number (a) 101, 1001)2, that is, a quadruple of decimal 59 is generated.

In this case, each digit of the input binary W-adic number is encoded by the encoding circuit 8 according to the rules shown in A4 of FIG.

Therefore, the shift circuit 3 has (1110, 1001)
2 is input, and (A) 001, 1101, 0010) 2, which is shifted to the left by 1 bit including the upper position digit, is given to the 6 adder circuit 5, where each digit is changed to (A) 110) 2.
It is added in advance. However, although a carry occurs from the second lower digit, this carry is not propagated to the higher digits and is discarded. Therefore, the output of the 6-adder circuit 5 is (0111,0011
,1000)2. On the other hand, the output of the shift circuit 4 is (a)001,0110,0100)2. Therefore, the addition result of binary arithmetic unit 1 is (1000, 1001, 1
100) becomes 2. In this binary addition, no carry occurs from any digit. Therefore, the subtraction circuit 6 subtracts (a)110)2 from all input digits, and the result is (0
010,0011,0110) 2 or decimal 2
It is 36. This is clearly four times the input binary coded one attack number. As for the digits that have been carried over by the binary addition in the binary arithmetic unit 1, the 6-subtraction circuit 6 outputs the input digits as they are, as shown in FIG. 4c.

Also, the encoding circuit 8 inputs digits (0101) 2, (011)
(0110) for each of 0)2 and (0111)2
2 may be output. However, in this case, when the 6-addition/addition circuit 5 adds, it is necessary to propagate the carry from each digit to the higher-order digits. FIG. 5 is a block diagram of a binary code/one attack conversion circuit to which the w-adic quadruple generation circuit according to the present invention is applied.

The part surrounded by the number 9 is the quadruple multiple generation circuit shown in FIG. Further lower than the least significant bit input of the shift circuit 4 is a 2-bit input, into which the carry bit (2 bits) of the 2-bit left shift circuit 10 is input. The shift circuit 10 receives a binary number to be converted into a binary W-adic number, and (a) 0) is inserted into its lower two bits. Further, the output of the m calculation circuit 7 (which includes a binary calculation unit, 6 addition circuits, and 6 subtraction circuits, as shown in FIG. 3) is returned to the encoding circuit 8. Next, the operation will be explained.

First, the binary number to be converted into a binary number is transferred to the shift circuit 1.
0, and the 1/4 multiple generation circuit 9 is cleared.

The shift circuit 10 shifts 2 bits to the left, and its carry bits, that is, the upper 2 bits of the input binary number, are inserted into the lower 2 bits of the shift circuit 4. Next, the immediately preceding output is input to the shift circuit 10, and at the same time, (a) and O) are inserted into the lower two bits. Next, shift circuit 10
The contents of are shifted 2 bits to the left, and 2 carry bits are inserted into the lower 2 bits of shift circuit 4. This operation is repeated until all binary numbers initially input to shift circuit 10 have been shifted to the left. On the other hand, 1 pheasant 4
The multiple generation circuit 9 executes the above-described operation every time the shift circuit 10 performs a shift operation, and returns its output to the encoding circuit 8 for use in the next operation. In this way, the binary w-adic number to be finally obtained as the output of the w-adic quadruple generation circuit 9 is obtained.

The binary-to-digital conversion circuit described here converts the binary number into B=B.
O, bl, l) 2...Bn, in w-adic representation, B=4(...4(4(4×0+tob1)+B
This takes advantage of the fact that it can be expressed as 2b3)+...)+Bn-1bn.

The 1-attack-4 multiple generation circuit of the present invention has the configuration described above, and the following effects can be obtained.

First, since the encoding circuit encodes each digit of the input binary w-adic number according to a predetermined rule without needing to refer to other digits, the encoding speed can be easily increased. The speed of multiple generation can be improved. For the same reason, when the encoding circuit is configured with logic blocks in units of digits or bytes, there is no need for communication between logic blocks, making it easier to implement each logic block. In addition, it is possible to effectively utilize the 1-digit calculation circuit (including the 6-addition/subtraction circuit) included in the processing device that handles binary-coded W-adic numbers.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional w-adic quadruple generation circuit;
The figure is a table showing the correspondence between input and output of the encoding circuit in Figure 1,
FIG. 3 is a block diagram showing an embodiment of a w-adic quadruple generation circuit according to the present invention, FIG. 4a is a table showing correspondence between input and output of the encoding circuit in FIG. 3, and FIG. 4b is A table showing the correspondence between the input and output of the 6 adder circuits in Figure 3, and Figure 4c is the 6 in Figure 3.
FIG. 5 is a block diagram showing an example of a binary w-adic number conversion circuit to which the w-adic quadruple generation circuit of FIG. 3 is applied. 1... binary arithmetic unit, 3, 4, 10... shift circuit,
5...6 addition circuit, 6...6 subtraction circuit, 7...1
Pheasant operation circuit, 8... encoding circuit.

Claims (1)

[Claims] 1. An encoding circuit that converts each digit of an input binary coded decimal number into a 4-bit code according to a predetermined rule, regardless of other digits, and an output of the encoding circuit. A first shift circuit that shifts one bit to the higher digit side and outputs it; a 6-addition circuit that adds (0110)_2 in binary to each digit of the output of the first shift circuit; and the input binary coded decimal number. a second shift circuit that shifts 2 bits to the upper digit side and outputs the result, a binary arithmetic unit that adds the output of the second shift circuit and the output of the six adder circuits in binary, and the binary arithmetic unit. Among the outputs, the digits that were not carried during the binary addition are output by subtracting (0110)_2 in binary, and the digits that were carried are output as is.6
1. A decimal quadrupling generation circuit, comprising: a subtraction circuit, and obtaining a quadruple of the input binary coded decimal number as an output of the six-subtraction circuit. 2 The encoding circuit converts each digit of the input binary coded decimal number to (0000)_2, (0001)_2, (001).
If either 0)_2 or (0011)_2, then (00
00)_2, and if it is (0100)_2 then (00
11) Convert to _2, (0101)_2, (0110)
If either _2, (0111)_2, then (1110
)_2, (1000)_2, (1001)_2
If it is either (1001)_2, convert it to (1001)_2 and
2. The decimal quadruple generation circuit according to claim 1, wherein the adder circuit is configured to discard carry from each digit.