JPS6049366B2 - push pull amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier having an all-stage push-pull configuration using field effect transistors (hereinafter referred to as FETs) of different polarities in the first stage.

This type of push-pull amplifier is characterized in that the complementary symmetry of the amplifier circuit cancels out distortion components generated within the circuit, resulting in an amplifier with low distortion.

However, when using an FET in the first stage, the FET
(7) Due to variations in ID and O, variations occur in the operating points of the active elements in the second and subsequent stages that are directly connected to the output point of the FET, and as a result, the operating currents of the upper and lower parts of the push-pull circuit differ and are output. This has the disadvantage that it is difficult to keep the offset voltage constant.

Therefore, in the past, consideration has been given to inserting a variable resistor between the drain of each FET and the power supply to adjust the fluctuations in the operating point due to variations in IDss.

However, in the above-mentioned conventional device, the first-stage FET becomes a resistive load, which causes the disadvantage that the bare gain of the amplifier is limited.For example, this is not used in amplifiers that require high gain, such as equalizer amplifiers. difficult to do.

This invention increases the gain of the amplifier by connecting a constant current circuit as a load to the first-stage FET, and also connects the drain of the FET to The purpose of this invention is to provide an amplifier that can maintain a constant voltage and prevent the above-mentioned problems caused by FET fluctuations, and will be described below based on illustrated examples.

That is, in the figure, Q1 and Q2 are N-channel, channel, and P-channel FETs whose respective gates are connected to each other and connected to the input terminal IN, and whose respective sources are mutually connected, and the drain of the N-channel FET QI is The drain of the P-channel FET Q2 is connected to the positive power supply +B through the bipolar transistor Q3 and diode D1 that constitute the constant current circuit, and to the negative power supply -B through the bipolar transistor Q4 and diode D2 that constitute the constant current circuit. ing.

The drain of the N-channel FET Ql is connected to the base of the PNP bipolar transistor Q5, and the drain of the N-channel FET Ql is connected to the base of the PNP type bipolar transistor Q5.
The drains of ETQ2 are connected to the bases of NPN bipolar transistors Q6, and the collectors of transistors Q5 and Q6 are directly connected to NPN and PNP output transistors Q7 and Q8, respectively, and the outputs are output via their respective emitter resistors Rl and R2. It is configured to provide an output signal at terminal 0UT.

Note that the series circuit of diode D3 and resistor R3 connected between the respective collectors of transistors Q5 and Q6 is a well-known bias circuit for determining the idle current of the push-pull output stage, and also connects the output terminal 0UT and the source of the FET. A resistor R4 coupled between the source and the resistor R5 connected between the source and ground constitute a negative feedback circuit. Next, the bases of transistors Q9 and QlO are connected to each other, and the base and collector of one transistor QlO are short-circuited, thereby forming a current mirror circuit and mutually forming a constant current circuit.

Similarly, the bases of transistors Qll and Ql2 are connected to each other, and one transistor. The base and collector of the star Ql2 are short-circuited to form a current mirror circuit and also form a constant current circuit. The collectors of transistors QlO and Ql2 are both coupled to output terminal 0UT via resistors R6 and R7. the law of nature,
Further, transistor Q9 and transistor Qll are both connected in cascode to the transistors Q5 and Q6. Note that a resistor R8 is connected between the positive power supply +B and the base of the transistor Q3, and a resistor R9 is connected between the base of the transistor Q3 and the emitter of the transistor Q5.
constitutes a part of the constant voltage source, and similarly, a resistor RlO connected between the negative power supply -B and the base of the transistor Q4, and a resistor RlO connected between the base of the transistor Q4 and the transistor Q
4 between the 6 emitters. The connected resistor Rll constitutes a part of a constant voltage source.

That is, a voltage equal to the sum of the forward drop voltage Vf of the diode D1 and the base-emitter voltage VBIC of the transistor Q3 is applied to both ends of the resistor R8.

Here, a DC negative feedback loop is configured by transistors Q3 and Q5, and R9/R8×(■
A constant voltage of f+■BE) will be generated. Also, in transistor Q5, ■I3lEl is connected between the base and emitter.
As a result, the drain voltage of FETQl is +B-((Vf+V8O)+R9/R8(■f
A voltage of +Vl3E)+■BE) will be applied. Here, both Vf<15VBE are approximately 0.6V, so the drain voltage of FETQl is +B-(1.8+1.
2×R9/R8).

Similarly, the drain voltage of FETQ2 is -B+(1.8+1
．． 2×RlO/R9).

In the above configuration, when a signal is applied to the input terminal 1N,
Its input signals are FETQl, Q2 and transistor Q5,
It is amplified by a push-pull amplifier circuit consisting of Q6 and output transistors Q7 and Q8, and is brought to an output terminal of approximately 0. On the other hand, since the collectors of transistors QlO and Ql2, which form part of the current mirror circuit, are connected to the output terminal "0UT" via resistors R6 and R7, it is assumed that the offset voltage at the output terminal moves in the positive direction, for example. Then, the collector current of transistor QlO is
The collector current of the transistor Q9 is smaller than the collector current of the transistor Qll. As a result, transistor Q
The base potential of 7 is lowered, and the offset voltage of the output terminal 0UT is also lowered. Therefore, the output offset voltage will settle to approximately ground potential. Furthermore, if the offset voltage at the output end moves in the negative direction, the output offset voltage will be increased by the opposite effect to that described above, and as a result, the output offset voltage will settle down to approximately the ground potential.

Further, the respective drain voltages of the first-stage FETs Ql and Q2 are held constant based on the positive and negative power supplies +B and -B by the action described above, and the drain voltages are stabilized.

As described above, this invention uses a constant current circuit as the load of the FET, so it is possible to obtain a large bare gain, and even though the constant current circuit is used as the load of the FET, the drain voltage can be reduced. It has the characteristic of being stable.

[Brief Description of the Drawings] The drawing is a wiring diagram showing an embodiment of the present invention.
2...Field effect transistor, Q3~Ql2・
...Bipolar transistor.

Claims (1)

[Claims] 1 In a device in which field effect transistors of different polarities are used in the first stage, the same input signal is applied to each gate of each field effect transistor, and the output of the field effect transistor is push-pull amplified and brought to the output terminal,
A constant current circuit using a bipolar transistor is provided between the drain of the field effect transistor and the power supply, and the voltage between the base and emitter of this bipolar transistor is used for push-pull amplification whose base is directly connected to the drain of the field effect transistor. A push-pull amplifier, characterized in that the drain voltage of each of the field effect transistors is held constant by a constant voltage source containing the base-emitter voltage of the bipolar transistor.