JPS6050069B2 - Transistor making method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of making a transistor having a first impurity region in a substrate a short distance laterally from a second impurity region.

Because it is easy to manufacture, field effect transistors (FETs)
) is expanding its application to integrated circuit technology.

The most common FET uses source and drain regions on the surface of a silicon wafer separated by a channel region. The current flowing through the channel is controlled by a gate electrode on the channel region separated by a thin silicon dioxide film. These devices are suitable for large scale integrated circuit fabrication because all source and drain regions can be formed simultaneously by impurity diffusion or implantation and relatively high packing densities can be achieved. One drawback is that the speed of electron operation is limited by the difficulty of creating short channels on which to precisely align the gate electrode. A device similar in structure to a FET is a lateral bipolar transistor in which the emitter and collector regions on the wafer surface are separated by a short base region.

The practicality of this device is limited by the difficulty of creating a sufficiently short base region on the wafer surface. According to the present invention, the problem of short channel or short base region formation is alleviated.

That is, a first mask having a first vertical end is formed on a semiconductor substrate, and thereby the first vertical end is held as a reference end in subsequent steps, and the first vertical end is controllably removes a portion of the first mask to define a second vertical end laterally separated by a controlled distance from the position of the first mask. The first end held as a reference end is used to define the position of the first impurity region in the substrate, and the second end is used to define the second impurity region. For example, when fabricating FETs with significantly shorter channels, a metal layer is formed on a wafer, silicon dioxide is deposited on a portion of the metal layer, and the exposed metal is oxidized.

Controlled etching of a portion of the silicon dioxide exposes a small portion of the unoxidized metal layer. Electrolytic plating of the exposed metal parts creates a significantly narrower gate electrode, so when the deposited SlO2 is removed, the metal oxide and remaining metal layer form the gate electrode. and,
Ion implantation into the source and drain regions is performed using the gate electrode as a mask. Since the gate electrode can be made so narrow, the channel region is correspondingly short, making it possible to use it at very high frequencies. What has been described above is an example of the application of the invention to field effect transistor work. The method of the invention is also applicable to the fabrication of other types of transistors, such as lateral transistors. 1 to 4 show a short channel FE according to an embodiment using the present invention.
The manufacturing process of T is shown.

Referring to FIG. 1, a transistor is formed on a silicon wafer 1.
0 and on which a thick silicon dioxide layer 11, known to those skilled in the art as a field effect insulating layer, is thermally grown.
A thin film 12, known as a gate oxide layer, is also thermally grown thereon. As is well known to those skilled in the art, it is assumed that a large number of FETs will be fabricated on the wafer 10 at the same time. According to one embodiment of the invention, the thickness is typically 20
00 angstrom aluminum metal layer 13
is formed on the oxide film by vapor deposition. Referring to FIG. 2, the wafer is masked and a layer of silicon dioxide 14 is formed on the portions of the metal layer 13 that are not masked.

Note that the mask causes layer 14 to have an edge 15 approximately in the center of gate oxide 12. Formed layer 14
covers a portion of the metal layer 13 and leaves a portion exposed.
The exposed portions of metal layer 13 are then oxidized by anodization, thereby forming metal oxide film 17, in this case aluminum dioxide. Since aluminum dioxide has a larger volume than aluminum, oxidation is performed using a part of the metal layer 13, and the end of the metal oxide film 17 comes into contact with the end 15 as shown in the figure. The wafer surface is then exposed to an etchant and the silicon dioxide surface is selectively etched.

The silicon dioxide film is exposed for a sufficient time to cause the end of layer 14 to move from position 15 to position 15'' as shown. The distance that the position of end 15'' thus moves laterally is Because the silicon etch rate is highly predictable, it can be made very short with high accuracy. For example, if a wafer is exposed to buffered hydrofluoric acid for a predetermined amount of time, the etchant will etch at a rate of 1100 angstroms per minute, and the lateral distance between edges 15 and 15'' will be Note that in forming the position 15'', the position 15 is held by the end of the metal oxide film 17.

j By partially etching the oxide film 14, an extremely small surface 18 of the unoxidized metal film 13 is exposed.
remains.

The wafer is then placed in a suitable solution for gold plating on surface 18 to form electrodes 19. Since the surface 18 is the exposed part of the metal wafer, it is the only part to be plated with metal. Electrode 19 may be nickel formed on aluminum surface 18 by electroless plating. Various other metals may be formed by electrolytic plating, and it is also possible to plate aluminum on aluminum using a non-aqueous solution. Referring to FIG. 4, a significantly narrow gate electrode 19 is produced by the electrolytic plating process as described above. Gate electrode 19 was plated on surface 18 in FIG. The next step is to remove the metal oxide film 17 by selective etching.
Expose the oxide layers 11 and 12 again (except for the parts covered by 19). Next, source and drain regions 21 and 22 are formed in the wafer 10 by ion-implanting the gate electrode 19 and the electric field application insulating film 11. It is believed that ion implantation is a process well known to those skilled in the art and does not require much explanation.

Impurity ions, such as phosphorus, may be irradiated onto the wafer and subsequently diffused to penetrate gate oxide 12 and form regions 21 and 22. A metal strip such as electrode 19 and a thick silicon dioxide layer such as layer 11 act as an effective mask to selectively infiltrate through only gate oxide 12 as shown, i.e. The ions are irradiated with sufficient energy to penetrate the gate oxide film 12, but the energy is insufficient to pass through the electrode 19 or the electric field application oxide film 11. Note that the source and drain regions 21 and 22 define a channel region 23 therebetween, the length of which is dictated by the gate electrode 19.

On the other hand, since the gate electrode 19 can essentially be formed to a desired thickness, the limit lies in the control when selectively etching back the oxide film 14 shown in FIG. Since this selective etching can be performed with an accuracy of less than a micron, the channel 23 in FIG. 4 can similarly have dimensions of less than a micron, and the gate electrode 19 can also be aligned with the same accuracy as the channel. Diffusion of the source and drain regions 21 and 22 following ion implantation can also be used to control the junction boundaries and thus the channel length, as is well known. Furthermore, large arrays of such field effect transistors can be fabricated simultaneously in a single wafer, as desired in creating high speed switching systems, logic circuits, memory systems, etc. Typical thicknesses for each layer are:

Gate oxide film 12 has a thickness of 50 to 2000 angstroms, for example 150 angstroms in one example. The electric field applying oxide film 11 is typically one-thick as the gate oxide film. Aluminum layer 13 is up to 2 microns thick, typically 2000 Angstroms.
If the desired channel length is 0.25 microns, layer 14 may be initially 1 micron thick and then etched back to 0.25 microns. As is well known, the thinner the gate oxide, the higher the substrate doping concentration generally needs to be. Typically the p-type substrate is doped to 3x1017 carriers/al and the source and drain regions are doped to 1019 carriers/al. For circuit operation, the source, gate, and drain must be separated and the metal conductors must be precisely attached. 5 and 6 are plan views of a wafer 10 at different steps in an example of a fabrication method for achieving this. FIG. 5 is a plan view essentially of FIG. A thin oxide region 12 is indicated by 12A, and a border 12A separates it from the field application oxide region 11. A border 15 marks the edge of the formed oxide 14 in FIG. 15. After etchback, the edge or border has moved to the position shown at 15''. This exposure step causes the metal surface 18 to assume the shape of a concave square. To create a convenient shape for the gate electrode,
The wafer is coated with photoresist with L-shaped windows 25. Thereby, the gate electrode metal is electrolytically plated on surface 18 only in the area within L-shaped window 25. Referring to FIG. 6, this results in an L-shaped gate electrode 19 to which a gate conductor 27 is conveniently attached.

Windows 28 and 29 are etched through thin gate oxide 12 to expose source and drain regions 21 and 22 of FIG. Metal conductors 30 and 31 are attached to these, respectively, and they constitute source and drain electrodes. Figures 7 through 10 illustrate another method of defining narrow channel regions.

Referring to FIG. 7, a wafer 31 has a silicon dioxide 32
and coated with a layer of aluminum 33. A polycrystalline silicon layer 34 is formed, which as before has edges that define one boundary of the channel region. The exposed aluminum is anodized to form an aluminum oxide layer 36 contacting the end 35.

However, silicon layer 34 is still oxidized to form silicon dioxide layer 37. The advantage of forming this layer 37 is that it can be easily and selectively dissolved and its depth can be precisely determined. The wafer is thus exposed in a SlO2 solvent and the layer 37 is removed to define an edge 35'', with the first edge 35 being held by the edge 36 of the aluminum oxide layer. .As aforementioned,
This exposure creates a small surface of aluminum on which the gate electrode 38 is electroplated, as shown in FIG. Referring to FIG. 10, layers 33, 34 and 36 are removed and gate electrode 38 is used as a mask to define source and drain regions 39 and 40 separated by a short channel region 41 as described above. be done. It is preferable that the silicon dioxide layer 37 be formed by anodic oxidation of the polycrystalline silicon layer 34 rather than thermal oxidation.

This may be done before, simultaneously with, or after the anodization of the aluminum layer 33. The aluminum oxide layer 36 is preferably sintered at 450 DEG C. to make it more resistant to shock impact. This is because it is assumed that buffer etching is used for selectively etching the silicon dioxide layer 37. The temperatures required for anodizing and sintering are low enough to avoid diffusion of aluminum into the silicon. It is clear that either the structure of FIG. 4 or FIG. 10 can be used as a bipolar transistor, in which case the source and drain regions are considered emitter and collector separated by a short base region.

Such transistors, known as lateral transistors, offer certain advantages over conventional vertical bipolar transistors with emitter diffusion in the base region. Another method of making lateral bipolar transistors is shown in FIGS. 11-13, 14, and 16. Referring to FIG. 11, p-type wafer 44
is coated with a thin silicon dioxide layer 45 and a silicon layer 46 formed. A silicon nitride mask 47 having edges 48 is formed over layer 46 by conventional masking techniques. Layer 47 then serves as a mask for the ion implantation of n-type collector region 50. Referring to FIG. 12, silicon nitride layer 47 is then selectively etched, thereby moving the edge of layer 47 a short lateral distance from location 4 and diffused collector region 50. Referring to FIG. Next, the silicon layer 46 in FIG. 11 is oxidized to form a silicon oxide film 51 in contact with the end portion 4'. As is well known, silicon nitride is heated at 160°C for 1 minute with a solution of H3PO4.
Selectively etched at a rate of 0-80 angstroms. Referring to FIG. 13, silicon nitride layer 47 is then removed by selective etching.

This is similar to the remaining silicon layer 46 in FIG. This results in end 48 corresponding to the same position shown in FIG.
A thick silicon dioxide layer 51 and a thin oxide film 45 having
only remains. Using layer 51 as a mask, emitter region 52 is then defined by ion implantation. It extends from the collector region 50 to the ends 48 and 4 of FIGS.
``They are separated by a length corresponding to the lateral distance of. Since the gate electrode is not automatically determined, this process is more suitable for making lateral bipolar transistors than FETs. However, gate alignment is done using FET
It can also be applied to the creation of Referring to FIGS. 14 to 16, in accordance with another aspect of the present invention, the wafer 6
A method of making a lateral bipolar transistor in 0 is shown.

First, a thin oxide film 61 and a thick metal layer 62 are formed. A thick silicon dioxide film 63 with mask edges 64 is then formed. An n-type collector region 66 is formed by ion implantation using layer 63 as a mask. Another metal layer 65 is then formed by electrolytic plating only on the exposed surface portions of metal layer 62. Referring to FIG. 16, layer 65 is in contact with silicon dioxide film 63 so that it has an edge 64).

Silicon dioxide film 63 and exposed metal tube 62 are selectively dissolved so that layer 65 is the only exposed metal. Next, another metal layer 67 is selectively formed on metal layer 65 by electroplating or an electroless process. The metal re-formed by electrochemical plating produces a layer of uniform thickness. Thus, the end of layer 67 is separated from end 64 by a short, predictable distance. Next, emitter region 69 is formed by ion implantation using end portion 68 for lateral definition. The thickness of the metal layer 67, of course, defines the distance between the emitter 69 and the collector 66, which again can be made very small and with high precision. Layer 62 is preferably a very thin layer of tungsten. Layer 65 is preferably electroplated nickel, and layer 67 is preferably a nickel layer formed by electroless plating. Tungsten can be selectively etched with a solution consisting of 0.1 mole potassium ferricyanide (K3FeCN6), 0.25 mole KH2PO4 and 0.23 mole KOH. The various metals and corresponding etchants mentioned above are also given by way of example with respect to conductivity and pouring process.

Diffusion may be used in some instances rather than ion implantation. Diffusion can also be used in conjunction with ion implantation.

[Brief explanation of drawings]

1 to 4 are cross-sectional views of a semiconductor wafer showing various steps of fabricating an FET transistor according to the present invention; FIGS. 5 and 6 are sectional views of a semiconductor wafer at different stages of the fabrication process Plan views of the transistors shown in Figs. 7 to 1
FIG. 0 is a cross-sectional view of a semiconductor wafer showing various steps for producing an FET transistor according to another aspect of the present invention, FIGS. 11 to 13 are views showing yet another example to which the present invention is applied, and FIG. 14 to FIG. 16 are diagrams showing yet another example to which the present invention is applied. [Explanation of symbols of main parts] “Claims” “Terms of detailed description of the invention”
Term "semiconductor substrate" in "Ming"
10 silicon wafers (also 5
) Wafer metal layer 13 Metal layer (or) Al
Mini layer first mask
14 layer (or) oxide film first vertical end 15 end (
or) position 2nd vertical end 15'' end (or) position metal membrane 18 surface (or) aluminum
nium surface (or)
Metal surface metal layer 19 electrodes (or) gate
Electrode first impurity region 21 source region (or) region second impurity region 22 drain region (or
) Region 1 mask (also 47 silicon nitride mask
(or) layer) silicon nitride layer second vertical end 4'end (or) position first impurity region 50n type collector region (
or) Diffusion collection second mask 51 silicon dioxide layer silicon dioxide
63 Silicon dioxide film (or)
Layer first impurity region 66n type collector region second end
68 End second impurity region 69 Emitter region.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a transistor in which a first impurity region (for example, 21) is separated from a second impurity region (for example, 22) by a short distance in the lateral direction in a semiconductor substrate (for example, 10), forming a first mask (e.g. 14) having a first vertical end (e.g. 15) on a substrate; forming a reference end at the position;
controllingly removing a portion of the exposed surface of the first mask, including a portion defining a first vertical end of the first mask, and a controlled distance from the location of the first end; Laterally spaced second vertical ends of the first mask (e.g. 1
5') having a first vertical end on the semiconductor substrate at a position corresponding to the position of the first vertical end of the first mask; forming a second mask having a second vertical end at a position corresponding to the position of the vertical end and not allowing impurities to pass therethrough; and forming first and second masks spaced apart from each other in the semiconductor substrate. an impurity region, the first impurity region at a position defined by the first end of the second mask, and the second impurity region defined by the second end of the second mask. A method for manufacturing a transistor, comprising the step of forming the transistor at a position defined by the method. 2. In the transistor manufacturing method described in claim 1, before the step of holding the reference end portion forms the first mask, the step of forming a metal layer (for example, 13) on the substrate; A method for manufacturing a transistor, comprising the step of oxidizing a portion of the metal film not covered by the first mask before removing the portion of the first mask. 3. In the method for manufacturing a transistor described in claim 2, the step of defining the second end portion is a step of exposing a part of the metal film (for example, 18), and only the part of the metal film where the metal is exposed. Metal layer (e.g. 19) to adhere
A transistor manufacturing method characterized by a process of depositing. 4. In the transistor manufacturing method described in claim 3, the impurity region is formed by ion implantation, and the deposited metal layer, which is the second mask, is used as an ion implantation mask. A method for producing a transistor characterized by: 5. The transistor manufacturing method described in claim 4, wherein the first mask is a silicon layer formed on a portion of a metal film, and the metal film is made of aluminum. Creation method. 6. In the method for manufacturing a transistor according to any one of claims 1 to 5, the first mask is made of a silicon layer, and the removing step includes forming the first mask by removing a part of the silicon layer. 1. A method for making a transistor, comprising the steps of forming silicon dioxide through well-controlled oxidation and selectively etching the silicon dioxide. 7. In the method for manufacturing a transistor according to claim 1, the step of forming a metal layer on an oxide layer on a semiconductor substrate includes depositing a relatively thick material layer on a part of the metal layer. a first mask having an exposed portion including a first vertical edge, thereby covering a portion of the metal layer;
oxidizing the exposed metal layer to form a metal oxide layer abutting a first vertical end of the first mask;
uniformly etching a desired portion of the deposited material layer forming a second mask of the first mask laterally spaced a controlled distance from the location of the first end; defining a vertical edge thereby exposing a portion of the metal layer that is not oxidized; depositing metal on the wafer surface; depositing the metal only on the exposed metal layer; by having a first vertical end at a position corresponding to the position of the first vertical end of the first mask, and a position corresponding to the position of the second vertical end of the first mask. forming a second mask as a gate electrode having a second vertical end on the semiconductor substrate; removing the deposited material layer; and implanting impurities into the wafer by ion implantation into the semiconductor substrate. first and second impurity regions separated from each other, the first impurity region at a position defined by the first end of the second mask, and the second impurity region located at a position defined by the first end of the second mask. the impurity has insufficient energy to penetrate the gate electrode, and the impurity has insufficient energy to penetrate the gate electrode to define the source and drain regions. A method of making a transistor comprising the steps of: acting as an implant mask; and forming metal connections to each of the source, drain regions and gate electrodes. 8. The method of making a transistor according to claim 7, wherein the wafer is a silicon wafer, the oxide layer is formed by thermally oxidizing the silicon, and the deposited material layer is a deposited material layer. A method for making a transistor characterized by using silicon dioxide. 9. A method for making a transistor according to claim 7, characterized in that the deposited material layer is silicon, and a portion of the deposited material layer is oxidized after deposition.