JPS6050084B2 - power amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power amplifier circuit that operates with almost the same power efficiency as in class B operation and does not generate switching distortion.

Conventionally, power amplifier circuits for audio use single-ended push pull (hereinafter abbreviated as SEPP).

) circuits are frequently used and have particularly good power efficiency.
A class B SEPP power amplifier circuit biased for 4-reflex 3B class operation is employed. However, in a class B SEPP power amplifier circuit, if the idling current is ignored during the positive half-cycle period of the input signal and during the negative half-cycle period of the input signal, the transistors that supply power to the load are different, and the input The switching of the transistor is performed in accordance with the switching between the positive and negative half-cycle periods of the signal, and there is a drawback that switching distortion occurs due to the carrier accumulation effect of the transistor.

The present invention has been made in view of the above, and eliminates the above-mentioned drawbacks, operates with almost the same power efficiency as class B operation, and operates in accordance with switching between the positive and negative half-cycle periods of the input signal. The purpose of this is to provide a power amplifier circuit that prevents transistors from switching and maintains all transistors in the on state even in the case of low impedance loads until high output power is generated, and does not generate switching distortion. The present invention will now be explained by way of examples.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. The power amplifier circuit according to the first embodiment of the present invention has a diode 3 between the emitter of the transistor 1 and the collector of the transistor 2.
and resistor 4, connect transistors 1 and 2 in an inverse Darlington connection, and transistor 2
The collector of is connected to the load 6 through the resistor 5, and similarly, a diode 9 and a resistor 10 are connected in parallel between the emitter of the transistor 7 and the collector of the transistor 8, and the transistors 7 and 8 are connected in an inverted Darlington connection. ,
The collector of transistor 8 is connected to load 6 through resistor 11 to form a SEPP power amplification circuit. This SEP
Resistors 12 and 13 that divide the voltage between the emitters 1 and 7 into two are further connected to the P power amplifier circuit, and the resistors 12 and 13
Using the voltage at the common connection point B, that is, the voltage between the emitters of transistors 1 and 7 divided into 112 as a reference voltage, the voltage at the load terminal A is passed through the input resistor 14 to the inverting amplifier 17 having the feedback resistor 16. The output voltage of the inverting amplifier 17 is inverted and amplified, and the output voltage of the inverting amplifier 17 is passed through the resistor 18 to the transistor 1.
Similarly, the output voltage of the inverting amplifier 17 is applied to the emitter of the transistor 7 through the resistor 19. Note that +B and -B are positive and negative power supply terminals, and 20
is a constant current circuit connected between the bases of transistors 2 and 8 to flow a bias current to the bases of transistors 2 and 8.

Further, the bias circuit 21 is set to flow a predetermined idling current to turn on transistors 1, 2, 7, and 8, and to cause the power amplifier circuit to perform class B operation when an unmanned power signal is received. The constant current circuit 20 is used to turn on the transistors 2 and 8 even when the idling current of the transistors 1 and 2 is set to a small value.
The resistance values of 4, 16, 18 and 19 are R,,R5,Rl
O9Rll9Rl29Rl39Rl49Rl69Rl8
and Rl9, R5=Rll, Rl2=Rl3, R
Set l8=Rl9.

At the time of unmanned signal, load terminal A1 point B1 resistor 18 and 19
The common connection point C with the two is completely at the same potential. Note that the potential at point B always maintains the intermediate potential of the voltage between the emitters of transistors 1 and 7. Let's say that a negative half-cycle input signal is now applied. The collector currents of transistors 7 and 8 increase to supply power to load 6 through resistor 11.

Then, the potential at point A changes to the (+) side with respect to the potential at point B, and the potential at point C changes to the (-) side with respect to the potential at point B due to the input resistor 14 and feedback resistor 16. do. On the other hand, as the input signal increases in the negative half cycle, the potential at the collector point D of the transistor 2 rises with respect to the potential at the emitter point E of the transistor 1, and the diode 3 has an on-state voltage of 0.
6V is no longer maintained, the voltage applied to diode 3 becomes 0.6V or less, and the emitter current of transistor 1 is divided into resistors 4, 12, and 18, and becomes the composite value of the current flowing through resistors 4, 12, and 18. Therefore, transistor 1 remains on.

A portion of the emitter current of transistor 1 flowing through resistor 4 decreases as the potential at point A rises. Furthermore, if the collector currents of transistors 7 and 8 increase, the potential at point A will further rise, and finally a current will flow through resistor 4 in the opposite direction (from the collector side of transistor 2 to the emitter side of transistor 1). flows. Due to the rise in the potential at point D, if we ignore the inverting amplifier 17, the potential at the emitter point E of transistor 1 will rise and transistor 1 will turn off, but due to the presence of the inverting amplifier 17, the potential at point C will become (-). The potential of the emitter of transistor 1 is pulled down and transistor 1 is maintained in the on state. At the same time, part of the emitter current of transistor 7 flowing through diode 9 flows through resistor 19 to compensate for the decrease in the emitter potential of transistor 1, maintain the emitter potential of transistor 7, and reduce the voltage between the emitters of transistors 1 and 2. has a value corresponding to the bias path 21, and the transistor 1 is always maintained in an on state even when a negative half-cycle input signal is applied. Furthermore, when diode 3 becomes reverse biased, the potential at point C moves to the (-) side, and the current flowing through resistor 5 is extremely small compared to the current flowing through resistor 11, so resistor 5 should be ignored. If resistance 4
, 14, 16 and 18 constitute a bridge circuit.

Therefore, resistors 4, 14, 16 and 18 are set as R4・Rl6=
If set to Rl4 and Rl8, the bridge will be balanced,
The potential of the emitter of transistor 1 with respect to point B is resistor 1
Even with an increase in the current flowing through transistor 1, the potential of the emitter of transistor 1 does not change from that at the time of the unmanned power signal, and transistor 1 enters an on state in which the same emitter current as at the time of the unmanned power signal flows. Furthermore, even if the above-mentioned relationship R4・Rl6=Rl,・Rl8 does not exist between the resistors 4, 14, 16, and 18, the emitter potential of the transistor 1 falls as described above and the transistor 1 is turned on. In this case, the emitter current of the transistor 1 is turned on with a value different from that of the emitter current of the transistor 1 at the time of the unmanned power signal.

Furthermore, the operation when a positive half-cycle input signal is applied is the same as above, and a detailed description of the invention will be omitted.
In this case, the equilibrium condition is RlO・Rl6:RlCRl
The constant current circuit 20 and the resistors 22 and 23 may be omitted if the idling current of the transistors 1 and 2 is set to a large value during the unmanned power signal.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

The power amplifier circuit according to the second embodiment of the present invention has two inverting amplifiers.
These transistors correspond to transistors 1 and 2, respectively. In this embodiment, instead of the inverting amplifier 17 of the power amplifier circuit of the first embodiment of the present invention, an inverting amplifier having an input resistor 14 and a feedback resistor 25 is used to convert the voltage at the load terminal A point with the voltage at point B as a reference. The output voltage of the inverting amplifier 26 is inverted and amplified at 26, and the output voltage of the inverting amplifier 26 is applied to the emitter of the transistor 1 through the resistor 27.

Similarly, with the voltage at point B as a reference, the voltage at the load terminal A point is connected to an inverting amplifier 29 having an input resistor 14 and a feedback resistor 28.
The negative output voltage of the inverting amplifier 28 is inverted and amplified by the resistor 3.
0 to the emitter of transistor 7. Therefore, in the power amplifier circuit of this embodiment, as in the power amplifier circuit of the first embodiment of the present invention, for example, when a negative half-cycle input signal is applied, an inverting amplifier is used. The output voltage of transistor 26 and the output voltage of inverting amplifier 29 change to the (-) side, and even when a reverse bias voltage is applied to the diode 3, the emitter voltage of the transistor 1 is pulled down to the (-) side and is turned on. In addition, the emitter potential of the transistor 7 is maintained at the current level by a portion of the emitter current of the transistor 7 flowing to the diode 9 flowing to the resistor 30.
The emitter potential of is also maintained, and transistor 7 also remains on.

Further, when a positive half-cycle input signal is applied, the same operation as described above occurs. Therefore, transistors 1, 2, 7, and 8 are never turned off but are always turned on, and no switching distortion occurs. Also transistors 1 and 7
The same thing can be done by dividing the base-to-base voltage into two to obtain the voltage at reference point B.

As explained above, according to the present invention, all transistors are not switched regardless of the polarity of the input signal, the magnitude of the load impedance, and the magnitude of the output voltage, and switching distortion does not occur. do not have. Further, if the idling current of each transistor is ignored, the transistors that supply power to the load are switched depending on the polarity of the input signal, and the power efficiency thereof operates with almost the same power efficiency as in the case of class B amplification operation. Furthermore, the inverting amplifier operates only when an input signal is applied, and does not affect the bias current when an unmanned signal is applied.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention. FIG. 2 is a circuit diagram of a second embodiment of the present invention. 1, 2, 7 and 8...transistor, 3 and 9...
...Diodes, 17, 26 and 29...Inverting amplifier, 21...Bias circuit.

Claims (1)

[Claims] 1. A parallel circuit of a first diode and a first resistor is connected between the emitter of the first transistor and the collector of the second transistor to connect the first and second transistors in an inverted Darlington connection, The collector of the second transistor is connected to the load terminal through the second resistor, and the parallel circuit of the second diode and the third resistor is connected between the emitter of the third transistor and the collector of the fourth transistor. and connect the third and fourth transistors in an inverted Darlington connection, and connect the collector of the fourth transistor to the load terminal through a fourth resistor;
A single-ended push-pull circuit is configured by applying a constant bias voltage between the bases of the first and third transistors, and dividing the voltage between the emitters or bases of the first and second transistors. The voltage at the load terminal is inverted and amplified by an inverting amplifier, and the output voltage of the inverting amplifier is applied to the emitters of the first and third transistors through respective resistors. circuit.