JPS6050348B2 - Exterior plating method for semiconductor devices - Google Patents
Exterior plating method for semiconductor devicesInfo
- Publication number
- JPS6050348B2 JPS6050348B2 JP55078203A JP7820380A JPS6050348B2 JP S6050348 B2 JPS6050348 B2 JP S6050348B2 JP 55078203 A JP55078203 A JP 55078203A JP 7820380 A JP7820380 A JP 7820380A JP S6050348 B2 JPS6050348 B2 JP S6050348B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- lead frame
- semiconductor devices
- semiconductor device
- exterior
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/04—Manufacture or treatment of leadframes
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Description
【発明の詳細な説明】 この発明は、半導体装置の外装メッキ方法に関。[Detailed description of the invention] The present invention relates to an exterior plating method for semiconductor devices.
するものである。半導体装置にはその製造面において、
個々に独立して製造されるものと、一枚のリードフレー
ム枠に連続して形成され、最終的に個々に分割されるも
のとがある。It is something to do. In terms of manufacturing semiconductor devices,
There are those that are manufactured individually and those that are continuously formed on a single lead frame and finally divided into individual pieces.
ここでは、後者を例にとつて、従来のものを説明する。
従来の半導体装置の外装メッキのリードフレームをメッ
キ治具に取り付ける方法を第１図に示す。Here, the conventional method will be explained using the latter as an example.
FIG. 1 shows a conventional method for attaching a lead frame for exterior plating of a semiconductor device to a plating jig.
半導体装置１を形成したリードフレーム２には孔３が設
けられ、この孔３はメッキ治具５から突出した接触端子
４に引つ掛けられる。A lead frame 2 on which a semiconductor device 1 is formed is provided with a hole 3, into which a contact terminal 4 protruding from a plating jig 5 is hooked.
メッキ治具５にはメッキ装置の槽の大きさに応じて、複
数のリードフレーム２が装填される。メッキの際に必要
な電流は、メッキ治具５より接触端子４を通じて、リー
ドフレーム２の孔３の接点からリードフレーム２へ供給
される。この従来の方法による場合、つぎのような欠点
がある。A plurality of lead frames 2 are loaded into the plating jig 5 according to the size of the tank of the plating apparatus. The current necessary for plating is supplied from the plating jig 5 to the lead frame 2 through the contact terminal 4 and from the contact point in the hole 3 of the lead frame 2. This conventional method has the following drawbacks.
１ メッキ治具５の形状が弱く、接触端子４も細い導線
であるため、リードフレーム２の自動装填が困難である
。このため、メッキ治具５にリードフレーム２を装填す
るのに手作業に頼らなければならず、加工費が高くなる
。２ 作業性の面で、接触端子４はせいせい１り−ドフ
レーム当り２ケ所となるため、リードフレーム２の固定
が不安定で、接触不良からメッキ不良となりやすい。1. Automatic loading of the lead frame 2 is difficult because the shape of the plating jig 5 is weak and the contact terminal 4 is also a thin conducting wire. For this reason, loading the lead frame 2 into the plating jig 5 requires manual labor, which increases processing costs. 2. In terms of workability, since there are only two contact terminals 4 per lead frame, the fixation of the lead frame 2 is unstable, and poor contact tends to result in poor plating.
３ メッキ治具５の接触端子４にもメッキが付着するた
め、一定期間ごとに再生が必要である。3. Since plating also adheres to the contact terminals 4 of the plating jig 5, it is necessary to regenerate them at regular intervals.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、メッキ治具への半導体装置の装填
自動化をはかり、メッキ治具の再生を不要にするととも
に、メッキ不良を生じない半導体装置の外装メッキ方法
を提供することを目的としている。以下、この発明の一
実施例を図面を参考に説明・する。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and aims to automate the loading of semiconductor devices into plating jigs, eliminate the need to recycle plating jigs, and eliminate plating defects. The purpose of this invention is to provide an exterior plating method for semiconductor devices. An embodiment of the present invention will be described below with reference to the drawings.
第２図に示すように複数個の半導体装置１を形成したリ
ードフレーム２は導電性の細線６により、この細線６を
撚り合わせて１ケ所以上て接触および固定される。リー
ドフレーム２はメッキ装７置の槽に合せて、たとえば数
十〜数百枚、細線６でつながれ、連続体 となる。その
連続体７は細線６によりメッキ治具５の接触端子４に連
結され、メッキ液中に吊り下げられる。この場合、接触
端子４はメッキ液に浸漬する必要はない。また、メッキ
に必要な電流はメッキ治具５より接触端子４を通り、細
線６を通じて、各リードフレーム２へ供給される。接触
端子４はメッキ液に入る必要はないので、メッキの付着
を受けることはなく、再生の必要はない。また接触端子
４はリードフレーム２の孔３とと無関係となるので、充
分な強度を有するものとして、細線６を強固に支持する
ことができる。しかもリードフレーム２は撚り合せた細
線６で固定されるため、メッキ作業中の衝撃によりはず
れることがない。すなわち、リードフレーム２は細線６
を介して接触端子４に安定良く吊時され、メッキ不良が
防止される。またリードフレーム２を自動的にならべ、
細線６で撚り合せる装置は、比較的簡単に準備できる。
な，お、細線６に安価な材質のものを選べは、その細線
は一度の使用て廃却してもよい。なお、この発明はリー
ドフレーム状の半導体装置の場合について説明したが、
個々に分離した半導体装置に外装メッキを施す場合にも
同様に実施することができる。As shown in FIG. 2, a lead frame 2 on which a plurality of semiconductor devices 1 are formed is brought into contact with and fixed at one or more points using conductive thin wires 6 by twisting the thin wires 6 together. For example, tens to hundreds of lead frames 2 are connected with thin wires 6 to form a continuous body in accordance with the tank of the plating device 7. The continuous body 7 is connected to the contact terminal 4 of the plating jig 5 by a thin wire 6 and suspended in the plating solution. In this case, the contact terminals 4 do not need to be immersed in the plating solution. Further, the current necessary for plating is supplied from the plating jig 5 to each lead frame 2 through the contact terminal 4 and the thin wire 6. Since the contact terminal 4 does not need to be immersed in the plating solution, it is not subject to plating and does not need to be regenerated. Further, since the contact terminal 4 is independent of the hole 3 of the lead frame 2, it has sufficient strength and can firmly support the thin wire 6. Moreover, since the lead frame 2 is fixed by the twisted thin wires 6, it will not come off due to impact during plating work. That is, the lead frame 2 has a thin wire 6
It is hung stably on the contact terminal 4 via the contact terminal 4, thereby preventing plating defects. Also, automatically align lead frame 2,
A device for twisting thin wires 6 can be prepared relatively easily.
Incidentally, if a cheap material is selected for the thin wire 6, the thin wire may be used once and then discarded. Note that although this invention has been described in the case of a lead frame-shaped semiconductor device,
The same method can be applied when external plating is applied to individual semiconductor devices.
以上のように、この発明によれば、メッキ治具への半導
体装置の装填自動化をはかりメッキ治具の再生を不要に
し、かつメッキ不良を生じない半導体装置の外装メッキ
方法が提供される。As described above, the present invention provides an exterior plating method for semiconductor devices that automates the loading of semiconductor devices onto a plating jig, eliminates the need to recycle the plating jig, and does not cause plating defects.
第１図は従来の半導体装置の外装メッキ方法を示す斜視
図、第２図はこの発明の一実施例にかかる半導体装置の
外装メッキ方法を示す斜視図である。
１・・・・・・半導体装置、２・・・・・・リードフレ
ーム、４・・・接触端子、５・・・・・・メッキ治具、
６・・・・・・細線、７・・・・・・連続体。FIG. 1 is a perspective view showing a conventional method for plating the exterior of a semiconductor device, and FIG. 2 is a perspective view showing a method for plating the exterior of a semiconductor device according to an embodiment of the present invention. 1... Semiconductor device, 2... Lead frame, 4... Contact terminal, 5... Plating jig,
6... Thin line, 7... Continuum.
Claims (1)
導体装置を形成したリードフレームまたは半導体装置単
体のリードフレーム部を導電性の細線で複数個つなぎ、
連続体を形成し、その連続体を上記細線でメッキ治具の
接触端子に連結し、メッキ処理を行なうことを特徴とす
る半導体装置の外装メッキ方法。1. When applying exterior plating to a semiconductor device, connect multiple lead frames on which multiple semiconductor devices are formed or the lead frame portion of a single semiconductor device with thin conductive wires.
A method for plating the exterior of a semiconductor device, comprising forming a continuous body, connecting the continuous body to a contact terminal of a plating jig using the thin wire, and performing plating processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55078203A JPS6050348B2 (en) | 1980-06-09 | 1980-06-09 | Exterior plating method for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55078203A JPS6050348B2 (en) | 1980-06-09 | 1980-06-09 | Exterior plating method for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS574150A JPS574150A (en) | 1982-01-09 |
| JPS6050348B2 true JPS6050348B2 (en) | 1985-11-08 |
Family
ID=13655455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55078203A Expired JPS6050348B2 (en) | 1980-06-09 | 1980-06-09 | Exterior plating method for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6050348B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035871A (en) * | 1983-08-08 | 1985-02-23 | Matsushita Electric Ind Co Ltd | Optical reader |
| JPS62108563A (en) * | 1985-11-06 | 1987-05-19 | Mitsubishi Electric Corp | Plating treater |
-
1980
- 1980-06-09 JP JP55078203A patent/JPS6050348B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS574150A (en) | 1982-01-09 |
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