JPS605066B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an insulated gate field effect integrated circuit device having high reliability.

A generally known insulated gate field effect integrated circuit device has a source and a drain disposed opposite to each other on one main surface of a semiconductor substrate, and a channel region extending between the source and drain. a gate insulating film,
The device includes a plurality of field effect transistors each having a gate electrode provided on a gate insulating film.

In an enhancement type transistor, the gate electrode is provided to cover the entire channel region from the source end to the drain end. In reality, when providing the gate electrode after forming the source and drain, it is necessary to allow for alignment margin during the gate electrode pattern formation process, so the gate electrode must be placed between the source and drain regions at both ends. It is formed so that it overlaps slightly with the . Furthermore, when impurities are introduced into the substrate to form sources and drains using the gate electrode as a mask after forming a gate electrode, as in the case of widely known silicon gate integrated circuits, impurities may be introduced during the heat treatment process. Due to the diffusion, the source region and drain region overlap the gate electrode by the amount of diffusion.
However, as the density of integrated circuit devices increases, the thickness of the gate insulating film tends to become thinner, and with this trend, dielectric breakdown of the gate insulating film has become a major problem as a cause of device failure.

It is a well-known fact that the breakdown voltage of an insulating film generally decreases as the film thickness decreases. Even if the power supply voltage applied to the device is determined in consideration of this breakdown voltage, a voltage higher than the breakdown voltage may be applied to the gate insulating film due to noise that inevitably enters from outside the device. Gate dielectric breakdown that occurs in this way is often seen as a short circuit accident between the gate and drain. The purpose of this invention is to
It is an object of the present invention to provide a highly reliable semiconductor integrated circuit device having an enhancement type insulated gate field effect transistor by eliminating such a short circuit between the gate and drain due to breakdown of the gate insulating film.

A semiconductor integrated circuit device of the present invention includes a semiconductor substrate, a source and a drain provided oppositely on one main surface of the semiconductor substrate, and a channel region extending between the source and drain. and a gate electrode provided on the gate insulating film at a distance from the source and drain.

According to this invention, since the gate electrode is provided apart from the source and drain, short-circuit accidents between the gate and drain due to breakdown of the gate insulating film are prevented, and therefore a highly reliable semiconductor integrated circuit device can be achieved. It becomes possible to obtain. In particular, the effect of the present invention on preventing breakdown of the gate insulating film is poor when increasing the density by reducing the thickness of the gate insulating film and shortening the channel length. Further, according to the present invention, since there is no overlap between the gate electrode, the source region, and the drain region, the capacitance between the gate and the source and the capacitance between the gate and the drain can be minimized.
Therefore, it is possible to obtain a high-performance semiconductor integrated circuit device that is more suitable for high-speed operation than the conventional one.

Next, this invention will be explained using figures.

Enhancement type included in conventional semiconductor integrated circuit devices. A plan view and a longitudinal sectional view of an insulated gate field effect transistor used as an insulated gate field effect transistor are also shown in FIGS. 1a and 1b, respectively. The vertical cross-sectional view is a view taken along the dotted line in the plan view. Source region 12 and drain region 13 and gate electrode 15 provided on the main surface of semiconductor substrate 11
It is formed so that it partially overlaps with the . For example, assume that polycrystalline silicon 15 is deposited on a P-type silicon substrate via a gate insulating film 14, and then phosphorus atoms are introduced into the substrate 11 using ion implantation technology. At the time of implantation, the source region 12 and drain region 13 do not overlap with the polycrystalline silicon 15. However, in order to make the implanted phosphorus atoms work effectively as donors, it is necessary to perform heat treatment, and this heat treatment process causes the phosphorus atoms to thermally diffuse both in the depth direction and in the lateral direction. The gate electrode 15 and the source region 12 overlap and the gate electrode 15 and the drain region 13 overlap as shown in FIG.
There will be overlap with It has been found that when there is such overlap, breakdown of the gate insulating film 14 occurs at the end on the source side above the drain region 13. The locations where the gate insulating film frequently breaks down are indicated by thick lines in FIG. 1a. Breakdown on the channel region 16 hardly occurs unless the gate insulating film has a defect in that region. Also source 12
It is also unusual for this to occur in a region inside the thick line in the figure, which overlaps with the gate electrode 15 of the drain 13. These facts are thought to cause breakdown of the gate insulating film when the gate voltage is low and the drain potential is high.

In many integrated circuit devices, the source and drain are designed to be interchangeable, so that when one is a drain, the other acts as a source, and when one is a source, the other acts as a drain. In such a case, destruction is likely to occur at the ends of the impurity-introduced regions in both the source and drain regions. Therefore, countermeasures against destruction of the gate insulating film for a typical integrated circuit device must consider both the source and drain regions. Furthermore, the shorter the channel length L is, the thinner the gate insulating film is, and the more easily breakdown occurs.
Although the mechanism of destruction has not yet been clarified, it has been found that increasing the distance between the gate electrode and the drain causes destruction and causes the cell to writhe. In other words, the electric field applied to the gate insulating film is 4.
By reducing the size, it is possible to prevent destruction.
In an embodiment according to the present invention, as shown in FIG.
5 is provided apart from the source 22 and drain 23. If the gate electrode is provided at a distance of 1 from the end of the drain region 23, the distance between the gate electrode 25 and the drain region 23 will be J. However, x is the thickness of the gate insulating film. At this time, the electric field within the gate insulating film caused by the potential difference between the gate and the drain becomes 4 times smaller in tox/zo than in the conventional structure. Therefore, short-circuit accidents between the gate and the drain due to breakdown of the gate insulating film are reduced compared to the conventional case. The larger the value of 1, the worse the effect.

Now if bx=400A and 1=4000A, tox/
Zode city proverb: o. 1, and the electric field applied to the gate insulating film is 0.1 times that of the conventional case. The gate electrode is used to induce free charge electrons in the channel region 26 by its voltage, and it is not allowed to make 1 unnecessarily large.

However, it has been experimentally confirmed that even if the value of 1 is about W, which is the middle value of the depletion layer 27 in the source region, there is no problem in the operation of the transistor. In the channel region in the depletion layer shown in FIG. 2 at the source and drain ends, the state is more likely to be inverted than in the center of the channel due to the influence of the electric field from the source or drain, so the gate electrode 25 is placed directly above it. It is thought that the transistor will operate without any problem even if it is not present. Now, the impurity concentration of the P-type substrate 21 is 7×1 and 5 impurities, and the impurity concentration of the N-type regions of the source 22 and drain 23 is 1×1. If this transistor is used with a pack gate voltage of -2V applied to the source 22 and the substrate 21, the inside of the depletion layer extending from the source side in this state is calculated to be W = 5200. It becomes △. In this situation 1=400
Even at 0 A, there was no problem with transistor operation. By separating the gate electrode from the drain region in this way, breakdown of the gate insulating film can be prevented, and therefore reliability can be greatly improved. Further, the gate electrode 25 is connected to the source region 22
Since the gate and drain regions 23 do not overlap with each other, the capacitances between the gate and the source and between the gate and the drain are reduced compared to the conventional case, and it goes without saying that this results in favorable characteristics. The embodiment shown in FIG. 2 is shown in FIG. 3 in the order of manufacturing steps. A silicon dioxide film 32 with a thickness of 1 mm and a silicon dioxide film 33 with a thickness of 450 Å are placed at predetermined positions on one main surface of a P-type silicon substrate 31 containing boron of 1 × 1 and 6 pieces as an impurity. first coated.

The silicon dioxide film 32 is a field insulating film, and the silicon dioxide film 33 is a gate insulating film. Thereafter, N-type polycrystalline silicon 34 doped with phosphorus is deposited on the silicon dioxide film 33 as shown in FIG. 3a. This polycrystalline silicon 34 is first deposited over the entire main surface of the silicon substrate to a thickness of 5000△ by vapor phase growth.
After that, the surface of polycrystalline silicon was heated to 2000A by thermal oxidation.
Then, a silicon dioxide film 35 is deposited. Thereafter, polycrystalline silicon is deposited by photo-etching, leaving only the portion that will become the gate electrode in the future. Thereafter, phosphorus atoms are implanted into the source region 36 and the drain region 37 using ion implantation technology at an acceleration energy of 150 Kev and a dose of 6×1 and 5 atoms/clump.
Note that FIG. 3 shows how two transistors are formed on the substrate 31. Thereafter, the substrate shown in FIG. 3a is immersed in a mixed solution of glacial acetic acid and nitric acid containing hydrofluoric acid and iodine, and the polycrystalline silicon 34 is etched away by 6000 Å from the sides. The etched state is shown in FIG. 3b. Next, by thermally oxidizing the substrate, silicon dioxide is deposited on the sides of the polycrystalline silicon, and at the same time, the source region 3
6 and the silicon dioxide film 38 on the drain region are made thicker. This thermal oxidation treatment is performed in a steam atmosphere of 900 qo for 30 minutes. During this process, phosphorus in the source region 36 and drain region 37 is activated and at the same time is thermally diffused in the lateral direction by about 3000 A. After that, a gate for electrode ejection is provided, and a wiring layer 3 is further formed with an aluminum film.
form 9. The integrated circuit device thus formed is shown in FIG. 3c. In this embodiment, the gate electrode 34
is formed separated from the source region 36 and drain region 37 by 3000Δ. Therefore, short-circuit accidents between the gate and the source or drain are prevented, and the reliability of the device is increased. In addition, the capacitance between the gate and source and between the gate and drain is reduced, and the characteristics of the device are improved compared to before. The case where polycrystalline silicon is used as the gate electrode has been described above, but molybdenum, tantalum, aluminum, etc. may also be used as the gate electrode.

In addition to the silicon dioxide film, a silicon nitride film, an alumina film, or a glass film may be used as the gate insulating film, or a stack of these films may be used.

[Brief explanation of drawings]

Figures 1a and 1b are a plan view and a cross-sectional view, respectively, for explaining a conventional insulated gate field effect transistor;
FIG. 3 is a sectional view for explaining a first embodiment and a second embodiment of the present invention, respectively. 11... Semiconductor substrate, 12... Source, 1
3...Drain, 14...Gate insulating film, 15...Gate electrode, 16...Channel region, 21...Silicon substrate, 22・
...Source, 23...Drain, 24...
...Gate insulating film, 25...Gate electrode, 27...
・Depletion layer, 31...Silicon substrate, 32...
・Silicon dioxide, 33...Silicon dioxide, 34...
...Polycrystalline silicon, 35...Silicon dioxide, 36...Source, 37...Drain, 38...
・Silicon dioxide, 39...aluminum film. Younger brother' figure 2 figure 3

Claims (1)

[Claims] 1. A semiconductor substrate, a source and a drain provided oppositely on one main surface of the semiconductor substrate, a gate insulating film deposited on a channel region extending between the source and drain, and the gate insulating film. and a gate electrode provided on a portion of the channel region spaced apart from the source and drain, and applying a pack gate voltage to the semiconductor substrate with respect to the source to deplete the respective depletion layers from the source and drain. A semiconductor integrated circuit device having an enhancement type insulated gate field effect transistor, characterized in that the transistor extends below the gate electrode.