JPS6051196B2 - semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory circuits, and more particularly to static semiconductor memory circuits.

Generally, a static type semiconductor memory circuit includes a pair of bit lines (BL, BL) extending along the Y direction, a large number of memory cells connected to be sandwiched between the pair of bit lines, and a pair of bit lines (BL, BL) extending along the Y direction. Line (BL, BL)
The basic components include a pair of load transistors inserted into each of the memory cells, and a word line extending in the x direction for selecting each of the plurality of memory cells.

Conventionally, in a semiconductor memory circuit with such a configuration, 2
These problems have been drawbacks in this type of semiconductor memory circuit. The first problem is that power consumption becomes unnecessarily large. This is because, in the semiconductor memory circuit described above, a steady current is always passed through one of the pair of load transistors to one of the pair of bit lines.
The second problem is that it is difficult to increase the access time. There are two causes for this second drawback. The first reason is that when reading information from an accessed memory cell to a bit line, the steady current is drawn through the transistor in the memory cell and at the same time information is transferred onto the bit line. This naturally puts a brake on the reading speed. The second cause is gm (mutual conductance), mainly the load transistor G. Examples include n. Generally, it is known that the larger G6 is, the better in order to improve access time. However, on the other hand, G. ．． It is also well known that in order to increase the size of the transistor, the size of the transistor itself must be increased. In this case, in order to increase the degree of integration, G. ．． Usually, the design is made in the direction of making the data smaller, and as a result, access time becomes a sacrifice. Therefore, in order to solve the above-mentioned problems, the present applicant proposed the following semiconductor memory circuit (first proposal JP-A-58-41 filed on the same date as the present application).
No. 484).

This includes a pair of bit lines, a memory cell engaged with the pair of bit lines, a pair of load transistors inserted into the pair of bit lines, and a word line for accessing the memory cell. In a semiconductor memory circuit, a pair of level converters are provided, and each of the pair of level converters converts the level of a logic signal appearing on one of the corresponding one of the pair of bit lines, and converts the level of the logic signal appearing on one of the corresponding one of the pair of bit lines to the control electrode of one of the corresponding one of the pair of load transistors. It is characterized by the fact that it is applied to

Thus, as mentioned above. The first and second problems are solved quite effectively. However, when looking at the access time, it was found that it could be made a little faster by making further improvements. Therefore, in response to the first proposal, a second proposal (Japanese Unexamined Patent Application Publication No. 58-41486 filed on the same date as the present application) was made in order to increase the speed a little more.

This is called "GTr. of a pair of load transistors. This is a semiconductor memory circuit (first proposal above) in which the current is apparently variable depending on the information at the time of access, and the conventional steady current is controlled according to the information (first proposal above). A pair of gate circuits engaged with the bit line is provided, the gate circuits are both turned off for a predetermined period by a gate pulse φ1 generated immediately after the start of the access, and 4 the pair of load transistors are connected to the gate circuits of the pair of gate circuits. The device is characterized in that it is substantially turned off when the device is turned off. However, according to this second proposal, as described later, the power supply ■ is turned off immediately after access.

. Since the bit line and the pair of bit lines are momentarily disconnected, a new drawback arises in that the bit line that should be charged to the H level does not quickly shift to the H level. This is a level change delay that does not cause any practical problems, but depending on the required performance, it is necessary to eliminate such delays so that the quickest level change can be achieved. . Note that the cause of the delay in transition to the H level described above will be explained in detail later. Therefore, an object of the present invention is to achieve low power consumption and to achieve the above-mentioned first and second aspects.
The purpose of the present invention is to propose a semiconductor memory circuit that further improves the access time in the previous proposal.

In accordance with the above object, the present invention provides, when a pair of gate circuits driven and controlled by the gate pulse φ1 described above are used as a pair of first gate circuits, a pulse generated at substantially the same timing as the gate pulse φ1 and A pair of second gate circuits are provided which are driven and controlled by a short gate pulse φ2, and each of the pair of second gate circuits is connected between the pair of bit lines and the power supply, and the gate pulse φ2 is connected between the pair of bit lines and the power supply. It is characterized in that the pair of bit lines are rapidly charged to the level of the power supply while the bit line is being generated. More preferably, a third gate circuit is provided, and the third gate circuit is connected to the gate. Pulse φ
2, the bit line is turned on to short-circuit the pair of bit lines.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing a general static type semiconductor memory circuit.

In this figure, BL and plane are a pair of bit lines, and a large number of memory cells MC are arranged in engagement with the pair of bit lines BL and the decoy. The pair of bit lines B
A pair of load transistors Ql and Q2 are also inserted into L and l, respectively. On the other hand, a word line WL is engaged with the memory cell MC, and a desired memory cell MC is captured by the bit line and the word line. Note that, although there are actually many memory cells, many pairs of bit lines, and many word lines, they are not shown. Further, each bit line pair is provided with a write buffer for writing information and a sense amplifier for reading information, but these are not shown. Now, suppose memory cell MC (
7) Assume that logic L is stored on the BL side (therefore, logic H on the l side), and that the memory cell MC is now accessed by the word line WL.

In this case, the state of each transistor is first logic L and H.
is stored as shown, so transistor 9 is on and transistor Q6 is off. and,
Since there is an access from word line WL, transistor Q3 and transistor Q4 are both turned on.
Then, both transistors Q3 and Q5 turn on, so the power supply ■.

. A current 1 flows through the transistor Q1 in a route indicated by a dotted line in the figure toward the earth GND. This current constantly flows as long as the memory cell MC continues to be accessed, and is the aforementioned steady current. This results in a waste of power consumption (the first problem mentioned above). On the other hand, during read access, since the read operation is performed while drawing this constant current 1 through transistors Q3 and 9, from the perspective of memory cell MC, not only the capacitive load on bit line BL but also this The read operation must be performed while also being subjected to a steady current load, making it impossible to increase the access time (the second problem mentioned above). Therefore, as mentioned above, the present applicant filed an application dated the same date as the present application (Japanese Patent Laid-Open No. 5
8-41484) (hereinafter referred to as the first proposed semiconductor memory circuit), the above problem was solved to some extent.

This first proposed semiconductor memory circuit focuses on the Gm of the load transistors Ql and Q2. In other words, GO is made variable as appropriate to improve power consumption and access time. Specifically, as mentioned above, regarding the improvement of access time, G. In addition, regarding power consumption, increase G. after the rise of the current 1. Make n small.
However, in general, this G. ．． is fixed and relatively small. The reason for the small size is to increase the packaging density. Therefore, in the first proposed invention, a level converter '1 is introduced to make this Gm variable as appropriate. There is a pair of level converters, each of which functions to convert the level of a logic signal appearing on one of the corresponding pair of bit lines BL and BL, and apply the level of the logic signal to one control electrode of the corresponding pair of load transistors. FIG. 2 is a circuit diagram showing a first example of the first proposed semiconductor memory circuit.

In this figure, the same components as in FIG. 1 are indicated with the same reference symbols. Therefore, LCl and LC in this figure
2 is a pair of level converters introduced by the first proposed invention. Level converters LCl and LC2 receive and level convert logic signals on bit lines BL and l, respectively, and transfer these to respective control electrodes of load transistors Q1 and Q2 (in the figure, FETs).
gate). The operation is as follows.

Using the explanation of FIG. 1 again, the transistor 9 side is L1
When the memory cell MC is accessed by the word line WL with the transistor α side in the H state, the current 1 described above first rises. Before this current 1 rises, the logic level of the bit line BL is not sufficiently pulled to L, but is rather at H level. The level H of this bit line BL is sufficiently converted by the level converter LCl, and a sufficiently high level H is applied to the gate of the load transistor Q1.
It is applied as a level. Then, the load transistor Q1 is sufficiently maintained in the on state.
(Gm large). In this on state, if the memory cell MC is accessed as before, the current 1 will rise rapidly. This current 1 flows through the transistors Q3 and Q3. The logic of the bit line BL is L.
fall towards. Then, level converter L
Since Cl sufficiently converts the logic level that falls to L, a sufficiently low L level is applied to the gate of the load transistor Q1. For this reason, the load transistor Q1 is rapidly turned off and thereafter maintains this off state (G.n small). It is extremely advantageous that load transistor Q1 is turned off quickly after accessing memory cell MC. I mean,
Since current 1 rapidly decreases as memory cell MC is accessed, from the perspective of memory cell MC, only the original capacitive load of the bit line exists during the information read operation; load) will no longer exist. This leads to improved access time and eliminates the second problem mentioned above. at the same time,
The fact that the current 1 rapidly decreases and remains almost zero leads to an improvement in power consumption and eliminates the first problem mentioned above. FIG. 3 is a circuit diagram showing a second example of the first proposed semiconductor memory circuit.

In this figure, the same components as in FIG. 1 are indicated with the same reference symbols. Therefore, the converter and converter are a pair of level converters introduced by the first proposed invention. The difference between these level converters LC and [C and the above-mentioned level converters LCl and LC2 is that G. The logic signal for changing n can be obtained from one's own side (self-feedback type) or from the other side (mutual feedback type). This focuses on the logical complementarity of the bit line pair BL,l in the memory cell MC. Therefore, the level converter LC in Fig. 3 is an inversion of the level (H-+L, L-H)
It has both functions. However, the operating principle and effects are almost the same as the semiconductor memory circuit shown in FIG. In the simplest case, both the level converter LC and the cell described above may be inverters. Further, since the level converters LCl and LC2 do not involve level inversion, it is sufficient to use two stages of inverters connected in series. Inverters are extremely common and F
Two ETs are connected in series. Its form is C
Even in MOS circuits, E (Errllancement)/D
(DepletionOn) type circuit may also be used. CMOS
In the case of a circuit, the steady current to the gate of the load transistor becomes almost zero, which is preferable in terms of power consumption. However, it uses an E/D type circuit! Even if the load transistor is used, the gate capacitance of the load transistor is extremely small compared to the bit line capacitance, so power consumption is hardly a problem. The present applicant has further proposed the second proposal mentioned above.

This is a further improvement on the access time in the first proposal. FIG. 4 is a waveform diagram for explaining the operating characteristics that the second proposed semiconductor memory circuit should have.

However, column d) in this figure is a waveform diagram for the semiconductor memory circuit of the first proposal (FIGS. 2 and 3), which shows that there is still room for improvement in access time. Access time means the time until the level difference between the bit line BL and the bit line exceeds a predetermined value, so d
) The access time should improve if the waveform BLBIx in the column is raised or lowered more sharply. In addition,
Column a) in FIG. 4 shows the waveform of the address signal oil externally applied to the row address input, that is, the word decoder, and column d) shows the level change of the word line WL. When a memory cell MC is accessed, the word line WL is switched from L to H level. Waveforms characterizing this second proposed invention are shown in columns c) and e) of Figure 4).

According to column e), the level difference between the pair of bit lines BL and the bit lines is sharp, and the access time is shorter than in column d). This shortening of the access time was achieved only because the gate pulse φ1 (column (e)) was introduced. The gate pulse φ1 is generated immediately after the start of access (when switching the row address input), and turns off the gate circuit for a predetermined period t.
This gate circuit is unique to the second proposed invention and is illustrated here. FIG. 5 is a circuit diagram showing an example in which a gate circuit according to the second proposed invention is incorporated into the circuit shown in FIG. In this figure, reference symbols φ1, G11,
G1. The other components except for are as already described. Here Gll and Gl. indicates a pair of first gate circuits, shown as transistors in the figure. According to the example described above, when the memory cell MC is accessed, the information L on the bit line BL is read out. Bit line B
Since the level of L moves toward L, the load transistor Q1 eventually turns off via the level converter LCl and maintains this off state. However, it is too late for the load transistor Q1 to turn off as described above, and as described above, during this time, the memory cell MC will draw the above-mentioned steady current unnecessarily. Therefore, the first of the pair
Gate circuits Gll and Gl2 are further introduced, and the power source 2 is maintained regardless of whether the load transistor Q1 is on or off.
. The connection with the computer shall be interrupted during the predetermined period t. Then, the memory processor MC can immediately lead the bit line BL to the L level without discharging any excess current (the steady current). At this time, since the gate circuit Gl2 is also turned off, charging on the bit write positive side is performed from the memory cell MC side. however,
After the bit line BL reaches a sufficiently low level at time t1 (Fig. 4), the gate circuit G at time T2 (Fig. 4)
Turn on ll and Gl2, and set bit line ■ to VcO.
Charge rapidly from the side (at this time, the load transistor Q
2 is also turned on). Note that even if the gate circuit Gll is turned on after time T2, the load transistor Q1
is already turned off and does not change the bit line BL(7)L level. By the way, the present invention has one advantage over the first proposal, of course, by making it possible to further shorten the access time compared to the semiconductor memory circuit according to the second proposal.

In the above explanation, only the steady current suppression in the bit line BL on the L level side has been considered. However, attention should also be paid to charging in the -bit try AW on the H level side. This is because when the bit line is currently set to H level, if the first gate circuit Gl2 in FIG. In this case, the bit line must be charged to the H level from the memory cell CM. However, in the memory cell MC,
As specifically shown in Figures 1 to 3, there is a high resistance Rh.
The power supply VO is connected through this Rh (in this example, the right Rh).
. Because charging must be done from the beginning, rapid transition to H level cannot be expected. This is the cause of impeding improvement in access time. It should also be noted that the presence of this high resistance Rh also causes what is called erroneous writing.

That is, the logic between the information of a memory cell MC selected by a certain word line and the information of a memory cell MC selected by another word line among a plurality of memory cells in the same bit line. If the opposite is true, then
The information on the H level side in the later selected memory cell MC is erased and rewritten by the information on the L level side in the previously selected memory cell MC. This is because, for example, referring to FIG. 3, the H level of the transistor Q6 is gradually formed through the high resistance Rh, while the L level of the transistor α side is immediately formed by the earth GND. it is obvious. In any case, the slow level change of the bit line to be shifted to the H level side has an adverse effect on the access time and erroneous writing.

The turning off of the load transistor in the first proposal and the turning off of the first gate circuit in the second proposal further aggravated such adverse effects. Therefore, the present invention proposes the following semiconductor memory circuit. FIG. 6 is a circuit diagram showing an example in which the present invention is applied to the second proposed circuit shown in FIG. In the tree diagram, all the components except for G2l, G22, G3, and φ2 in the center are already explained. That is, a pair of second gate circuits G2l, G2. , third gate circuit G3, and gate pulse φ2 are the constituent elements that characterize the present invention.
The operation of the semiconductor memory circuit according to the present invention is as follows, and will become clear with reference to FIG. FIG. 7 is a waveform diagram used to explain the operation of the semiconductor memory circuit shown in FIG. 6. However, columns a), b) and d) in FIG. 7 are exactly the same as columns a), b) and c) in FIG. 4. What should be noted here is the gate pulse φ2 in column e), which is generated at the same timing as the gate pulse φ1, but its pulse width is shorter than that of the gate pulse φ1. This gate pulse φ2 is shown in Figure 6. A pair of second gate circuits G
When applied to 2l and G22, they both turn on and are directly connected to the power supply ■Cc. Therefore, even if the bit line is temporarily disconnected from the power supply by turning off the first gate circuits Gll and Gl2, the second gate circuits G2l and G2
. When turned on, it is rapidly charged to the power supply Vcc level. In this way, the bit line surface that is about to be charged to the H level is rapidly charged (on the contrary, the bit line BL surface
(The same applies when the data is charged to H level), the access time is improved and the above-mentioned erroneous writing is eliminated. In this case, since the bit line BL is in a state of being pulled to the L level, it seems useless to turn on the second gate circuit G2l and try to pull the bit line BL also to the H level. In other words, H level in a pair of bit lines! One may wonder whether it is sufficient to turn on only the second gate circuit (G2l or G2.) connected to the bit line on the side that pulls up to θ. However, the gate pulse φ2 is instantaneously generated immediately after access, and each time, one of the second gate circuits is selected and applied only to the corresponding second gate circuit. It's annoying to do. And even if you did, there wouldn't be much of an advantage. I mean,
Even if an H level is instantaneously applied (during φ2) to a bit line that should be set to L level, the l/transistor 9 or q on the side that should be set to L level is directly connected to the ground GND, and the bit line that should be set to L level is This is because it can be completed at a fairly high speed. In any case, the bit line that transitions to H level slowly due to the presence of high resistance Rh,
It is significant that the H level is forcibly applied from the outside. The present invention further preferably provides a third gate circuit G
3 will be provided.

This third gate circuit G3 is also turned on by the gate pulse φ2, and its role is to short-circuit the bit line BL and the gap. Anyway, as mentioned above, H
The purpose of the present invention is to quickly make the transition from the L level to the H level, and since the transition from the L level to the H level takes the longest time, the pair of bit lines BL and ? Immediately after access, both lines BL, ? If they are short-circuited, the potential on the L level side will be charged somewhat faster by the H level potential of the other side, and the transition to the H level will be completed more quickly. In addition, shorting both bit lines BL and l in this way means that both bit lines are reset each time they are read, and the levels of both bit lines are divided into upper and lower levels from a constant level P in column f) of Fig. 7. It turns out.

By ensuring that the level changes always start from a constant level P, the bit line can be uniformly reset to level P regardless of the level of the bit line immediately before the access, which is advantageous for improving access time. become. In other words, regarding the same bit line, 3H
When switching from the warm level to the L level, (
The switching time required from H to L) can be shortened to the switching time from a constant P level to an L level (P-+L). This is because the level base (1P on l) is the level difference (
This is because it is smaller than 1H1). Column f) in Figure 7 is the fourth
Column e) in Figure 7 and column c) in Figure 7 correspond to column d) in Figure 4, but c) and f) in Figure 7 correspond to column d in Figure 4.
) and e), the waveform change is expressed differently.
However, there is no essential difference. Column c) in FIG. 7 shows the conventional level change, whereas column f) in FIG. 7 shows the level change when the access time is improved by the present invention. show. As described above, according to the present invention, a semiconductor memory circuit with low power consumption, fast access time, and no write errors can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a general static semiconductor memory circuit, FIG. 2 is a circuit diagram showing a first example of the first proposed semiconductor memory circuit, and FIG. 3 is a first proposed semiconductor memory circuit. 4 is a waveform diagram for explaining the operating characteristics that the semiconductor memory circuit of the second proposal should have, and FIG. 5 is a circuit diagram showing the second example of the semiconductor memory circuit of the second proposal. 6 is a circuit diagram showing an example in which the gate circuit according to the proposed invention is incorporated; FIG. 6 is a circuit diagram showing an example in which the present invention is applied to the second proposed circuit shown in FIG. 5; FIG. FIG. 3 is a waveform diagram used to explain the operation of the semiconductor memory circuit shown in the figure. MC...Memory cell, BL, anus...Bit line pair, Ql, Q2...Load transistor pair, LCl9LC29LC, [d◆●●◆●●Level converter, WL...Word line, Gll, Gl
2...First gate circuit, G2l, G22...
...Second gate circuit, G3...Third gate circuit, φ1, φ2...Gate pulse.

Claims (1)

[Scope of Claims] 1. A pair of bit lines, a memory cell engaged with the pair of bit lines, a pair of load transistors each inserted into the pair of bit lines and connected to a power supply, and a pair of load transistors that connect the memory cell. It has a word line for access and a pair of level converters, each of which converts the level of a logic signal appearing on one of the corresponding one of the pair of bit lines to connect the corresponding one of the pair of load transistors. A pair of first gate circuits are provided to apply the voltage to one of the control electrodes of the bit lines, and are respectively engaged with the pair of bit lines, and the pair of first gate circuits are configured to generate power for a predetermined period immediately after the start of the access. In the semiconductor memory circuit, the pair of second gate circuits is configured to be turned off by a gate pulse φ_1, and to substantially turn off the pair of load transistors by turning off the pair of first gate circuits. The pair of second gate circuits are each inserted between the power supply and the pair of bit lines, are generated at approximately the same timing as the gate pulse φ_1, and have a shorter pulse width than the gate pulse φ_2. A semiconductor memory circuit characterized in that both are turned on. 2. The semiconductor memory circuit according to claim 1, further comprising a third gate circuit connected between the pair of bit lines and turned on by the gate pulse φ_2.