JPS6051200B2 - UV-erasable nonvolatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultraviolet erasable nonvolatile semiconductor memory.

Generally, among PROMs (programmable read-only memories), EPROMs (erasable PROMs) can be erased by ultraviolet rays and electrically rewritten by the user.
Due to its convenience, it has recently been widely used as memory for microcomputers and the like.

Figure 1 shows a part of a conventional example of such an EPROM, where 10 to 1n are row decoders each using an insulated gate field effect transistor (for example, MOS-FET), and O to No are the same row decoders. In the row buffer circuit using MOS-FETs, 1 to 1 are row lines of a memory cell array 4 using nonvolatile semiconductor memory elements. The row decoders 10 to 1n each receive address data A. −
Ai is included, and this data A. -Ai's''
One of the row lines is selected and driven by a combination of 1'' and 0'', and the selected row line becomes active ('1'' level). That is, when the address data ~Ai are all "o", the row line F is selected, and when the address data Ai=0, the row line & is selected. In the above-mentioned row buffer circuits B to No, 5 is a write circuit that supplies a write voltage (for example, a high voltage of 20 to 25 V, and a so-called program pulse) to the corresponding row line B to No when writing to the memory cell array 4. It is a circuit. By the way, when erasing the memory contents of the memory cell array 4, it takes a considerable amount of time (approximately 3 hours), and moreover, the memory contents of all memory cells of the memory cell array 4 are erased.

For this reason, conventionally, even when it is desired to rewrite only a part of the memory contents of the memory cell array 4, it is necessary to erase the contents of all the memory cells and then write to all the memory cells again. As mentioned above, the erasing time alone is disadvantageous in that it requires a long time. The present invention has been made in view of the above circumstances, and uses a non-volatile semiconductor memory element in which a spare memory cell is provided in a part of a memory cell array and address data for selecting this memory cell can be written. By providing a spare decoder, a part of the memory cell array can be rewritten easily and in a short time, and the yield rate of non-defective products at the manufacturing stage can be improved. It provides:

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In Figure 2, 10 can be erased with ultraviolet light.

It is a memory cell array that uses nonvolatile semiconductor memory elements that can be electrically rewritten and electrically rewritten.In addition to the normally used main memory cell area M, there is also a spare memory cell area S (partially used for rewriting). For example, two rows of memory cells)
It has RO~! Rn is a row line of the main memory cell area, and R1'' and R2'' are row lines of the spare memory cell area S. And the row lines R1~ of the main memory cell area M
Corresponding to Rn, a decoder 1 similar to that in FIG. -1n and a row buffer circuit B-1n are provided, and spare row decoders 11, 12 and spare row buffer circuits 13, 1 are provided corresponding to row lines R1'', R2'' of the spare memory cell area S.
4 is provided. In the spare row decoders 11 and 12, 2(1+1) nonvolatile semiconductor memory elements, such as floating gate type memory cell transistors T, are provided. -Ti, TJ-Ti'' are connected in parallel, and address data ~Ai and brother ~Ai are applied to their gates. Also, the transistors T.-Ti, TO'
A gate is connected between the connection line 15 of ~Ti'' and the
A depletion type transistor T whose source is connected.
and an enhancement type transistor TIl: are inserted, and an enhancement type transistor TE'' is inserted between the connection line 15 and the power supply terminal 16.
A signal R that becomes O■ when writing an address is applied to the gate of
/F (R/F in decoder 11; R/F in decoder 12;
P2) is applied to the gate of the transistor TE'', and a signal k/P1 (k/P1 in the decoder 11, 'R/P2 in the decoder 12) which becomes a high voltage (for example, 25 V) when writing an address is applied to the gate of the transistor TE''. On the other hand, the spare row buffer circuits 13 and 14 have the same configuration as the normal row buffer circuits. moreover,
The normal row decoder 1.

The drains and sources of two transistors TA and TI3 are connected between the decode output line G-hole of ~1n and the ground terminal, and each gate of the transistor TA group is connected to the spare row buffer circuit 13. is connected to the output terminal of the spare row buffer circuit 14 by a signal line 7, and each gate of the transistor TB group is connected to the output terminal of the spare row buffer circuit 14 by a signal line 8. Note that 16 is a column decoder for selecting a column line of the memory cell array 10, and illustration of other peripheral circuits is omitted.

Further, the memory shown in FIG. 2 is manufactured by an N-channel process. Next, the operation of the nonvolatile semiconductor memory with the above configuration will be explained.

For normal writing, input data is set and row decoder 1 is input. .about.1n indicates the row line R of the main memory cell area M. -Rn
is selected and the row buffer circuit Z-additional write circuit (first
A write voltage (2) is applied to the memory cell (see FIG. 5), and input data is written into the memory cells of the main memory cell area M. Next, when part of the written content is to be rewritten as described above, an address that requires rewriting is specified using address data, and this address is assigned to a row line of the spare memory cell area S. That is, for example, row line R. When rewriting the stored contents of the memory cell, address data A is used. −
Set the Aj input to ゜“0゛, the ``AO-''Ai input to a high voltage (for example, 25V), the R/F1 input to ゜“0゛, the k/P1 input to a high voltage (for example, 25V), and connect the power terminal 16.
If a high voltage (for example, 25V) pulse is applied to the transistor TE, the transistor TE is turned off,
is turned on and the floating gate transistor T to which the XO-'Ai input is applied. A high voltage is applied to the drain and gate of ``~Ti'', and electrons are injected into each floating gate.As a result, the transistor T''~Ti'' has a gate input voltage in the range of O~■C. Now we are in the cutoff state, and the row line R
1'' is assigned the address of A.-Ai=゛゜0゛.Therefore, after this, the
゛, N1 = “1゛ (Vc), R/F, =゛゜1゛,
If the normal P1 is set to "0" and the read state is entered, the decoded output of the spare row decoder 11 becomes "1" and the row line R1" is selected, so the line corresponding to this row line R1" is selected. Write circuit of spare row buffer circuit 13 (see FIG. 1, 5)
By applying a write voltage p to the row line R1
It is possible to newly write input data that is separately given to the memory cell of ``, and equivalently, it is possible to rewrite the memory contents of the memory cell connected to the row line R of the main memory cell area M. For the memory cell array 10 that has been partially rewritten without erasing all the memory contents of the memory cell array 10, ~Ai="゜0
When the "1" address is specified, the spare row decoder 11 and the spare row buffer circuit 13 automatically select the row line R/ of the spare memory cell area S, and at this time the "1" output of the spare row buffer circuit 13 is automatically selected. The transistor TA, which is applied to the gate via the signal line 7, turns on and stops the row decoder 10 from selecting the row line R of the main memory cell area M.Similarly, the spare row decoder 12 and the spare row buffer circuit 14 as required.

-Ai- When writing is performed by assigning an address other than "゜0'゛ to the spare memory cell area Sσ row line R2", the memory cell in the -゛memory cell area M with the same address as this assigned address is Rewriting can be performed easily and in a short time without completely erasing the memory cell array. In the above embodiment, two rows of spare memory cells are provided, but the invention is not limited to this. Three or more rows of memory cells are provided, and correspondingly, spare row decoders 11 and 12, spare row buffer circuits 13, 14. By adding the signal lines 7 and 8 and the transistors TA and TB, the rewrite capacity can be increased.

Further, when a plurality of (j) rows of spare memory cells are provided, the row decoder 1 is used. Signal lines 7 and 8 in each of ~1n
, one transistor TA, one transistor TB, respectively, as shown in FIG. Alternatively, the signal may be inverted and sent to the common signal line 32. That is, this signal line 32 corresponds to the signal line 7 or 8. In addition, the nonvolatile semiconductor memory elements of the memory cell array 0 and the spare row decoders 11 and 12 in the above embodiments may be floating gate transistors or devices having the same function as the floating gate transistors. Other transistors having capture means, such as MNOS (metal nitride oxide semiconductor) type transistors in which Sj3N4 (silicon nitride) is provided between an SjO2 (silicon oxide) film and a polysilicon layer, or fuse blowing type transistors Memory cells or a combination thereof can be used. This invention is particularly effective in the case of a fuse blowing type PROM. With the fuse blowing type, once writing is performed, it cannot be rewritten. Therefore, even if it becomes necessary to rewrite the memory contents of some memory cells,
It is necessary to newly write into a separate fuse-blown PROM (5).Each time a part of the memory contents is changed, a new one must be used. If the above function is provided, even in a fuse blowing type PROM, the stored contents of only a part of the memory cell can be rewritten, and there is no need to use a different one every time a part is rewritten 4θ. Further, in the above embodiment, spare memory cells are provided for memory cells in the row line direction of the main memory cell area, but spare memory cells are provided for memory cells in the column line direction of the main memory cell area with respect to 0C1-. Good too.

In this case, a spare column decoder may be provided to select a column line in the spare memory cell area, and the selection output of this spare column decoder may be used to inhibit the selection output of the column decoder corresponding to the main memory cell area. . As described above, according to the nonvolatile semiconductor memory of the present invention, a spare memory cell area is provided in addition to the main memory cell area as a memory cell array, and a memory cell area for selecting a row line or a column line of this spare memory cell area is provided. A spare row decoder or a spare column decoder using a nonvolatile semiconductor memory element is provided,
Address data corresponding to memory cells that require rewriting in the main memory cell area is written to a spare row decoder or a spare column decoder, and the row decoder corresponding to the main memory cell area is written by the selected output of this spare row decoder or spare column decoder. Alternatively, selective output of the column decoder is prohibited.

Therefore, the user can easily rewrite only a portion of the memory content in the memory cell array without erasing all of the memory content, which saves the relatively long time traditionally required for erasure. Can be significantly shortened, EP
This makes the use of ROM even more convenient.

Also, on the manufacturer side, when manufacturing an EPROM, if a part of the memory cells, for example, one memory cell, cannot be written to, the EPROM is treated as a defective product, but according to the present invention, the defective memory Write to the spare decoder to select a spare memory cell in the spare memory cell area instead of the cell (address program)
By doing so, the EPROM can be treated as a good product and the yield can be improved.

In this case, an ultraviolet-erasable memory element is also used in the spare decoder, and an arrangement is made to prevent the contents of the spare decoder from being erased when the memory cell array is irradiated with ultraviolet light. That is, the preliminary decoder part is covered with a metal such as aluminum that does not transmit ultraviolet rays so as to prevent ultraviolet rays from irradiating the memory element. As described above, the present invention not only allows partial rewriting of a memory cell array using non-volatile semiconductor memory elements easily and in a short time, but also provides an ultraviolet erase type that can improve the yield rate of non-defective products at the manufacturing stage. Non-volatile semiconductor memory can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a conventional nonvolatile semiconductor memory, FIG. 2 is a configuration explanatory diagram showing an embodiment of a nonvolatile semiconductor memory according to the present invention, and FIG. 8 and transistors T9 and TO; FIG. 10 to 1n... row decoder, 5... writing circuit,
Snake~Button...Decode output line, 10...Memory cell array 11, 12...Spare row decoder, 16...Column decoder, RO-Rn, Rl'', R2''...Row line, TO
-Ti, TO゛~Ti''...Floating gate transistor, M...Main memory cell area, S...Spare memory cell area.

Claims (1)

[Claims] 1 A memory cell array using a first ultraviolet erasable nonvolatile semiconductor memory element and having a main memory cell area and a spare memory cell area, and selecting row lines and column lines of the main memory cell area by inputting address data. a row decoder and a column decoder, which are provided corresponding to row lines or column lines of the spare memory cell area, and have the same structure as memory elements in the memory cell array in which address data of the main memory cell area can be written. a second ultraviolet-erasable nonvolatile semiconductor memory element; a light shielding means for covering the second ultraviolet-erasable nonvolatile semiconductor memory element to prevent the memory element from being irradiated with ultraviolet rays; A spare row decoder or a spare column decoder to which address data to be written to the erasable nonvolatile semiconductor memory element is supplied, and a row line or column line for the main memory cell area and a row line or column line for the spare memory cell area. a write circuit for supplying a write voltage when writing data to the first ultraviolet erasable nonvolatile semiconductor memory element connected to each corresponding row line and column line; and the spare row decoder. Alternatively, an ultraviolet-erasable nonvolatile semiconductor memory comprising: inhibiting means for prohibiting establishment of the selection output of the row decoder or column decoder for the main memory cell area when the selection output of the spare column decoder is established.