JPS605225B2 - Electrode structure of semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor devices, particularly in electrode portions of semiconductor devices.

Conventionally, for example, a P-channel MO with a silicon gate
In ICs, LSIs, etc. including SFETs, etc., the structure shown in FIG. 1 has been adopted as the electrode structure thereof.

That is, the normal phosphorus glass (PSG) provided on the surface of the Si substrate 1
protection (passivation) waist consisting of
An AI pad 3 is formed thereon.

Although not shown, this safety pad 3 is connected to an AI wiring layer provided on the protective film 2. A PSG layer 4 is used to protect this AI pad and the above-mentioned AI wiring layer.
And a polyimide resin (abbreviated as PIQ) film 5 is provided. This double film of PSG layer 4 and PIQ film 5 is made of AI
A hole is made on the pad 3 to expose the central portion of the N pad 3. A double layer usually consisting of a NiCr layer 6 and a Pd layer 7 is adhered to the exposed AI pad 3, and then an Au layer is placed on top of this double layer.
A plating layer 8 is provided. The Au plating layer is a bump,
The metal layers 6 and 7 directly below the Au plating layer are called under bump metal (UBM) layers. A lead wire such as a bonding wire or a carrier tape is bonded to the Au bump 8 by thermocompression.

When mass producing semiconductor devices such as ICs and LSIs having electrodes having such a structure, accidents such as defects in the A board and defects in the protective film often occur, lowering the manufacturing yield.

As a result of investigating the causes of such defective accidents, the inventors came to the following conclusion. Because of the poor adhesion between the under bump metal layer and the PIQ layer, even if the etch time is slightly longer than the specified value, the etchant will penetrate to the phantom pad and corrode the AI pad.

Furthermore, as is clear from the structure shown in FIG.
The AI pad 3 is placed below, and if the lead is bonded (thermo-compression bonded) to the bump 8 with this structure, a considerable pressure is applied from above, so the AI pad 3
The glass film will crack in the area where it overlaps. Therefore, an object of the present invention is to propose a semiconductor device having a highly reliable electrode structure that does not cause corrosion of the AI pad or cracking of the glass protective film.

The present invention focuses on the cause of the above-mentioned defective accidents, and the under-bump metal layer is coated with a glass protective film "for example, SiO2".
, PSG, etc. and a polyimide resin (PIQ) protective film.
The I-pad is characterized by a structure that does not include a glass protective film that is easily broken. That is, the electrode structure according to the present invention includes an AI pad provided on the surface of a semiconductor substrate with a protective film interposed therebetween, and a glass protective layer formed around the AI pad without overlapping the AI pad. and an under bump metal layer formed such that the center part is in close contact with the upper surface of the AI pad and the peripheral part is in close contact with the glass protective layer, and the center part of this metal layer is exposed and the peripheral part and the above-mentioned It consists of a polyimide resin film formed to cover the top surface of the glass layer, and a metal plating layer formed in close contact with the center of the exposed under bump metal layer.

An embodiment of the present invention will be described below.

FIG. 2 is a sectional view of a particularly improved electrode portion of a semiconductor device according to the present invention.

In the figure, the same symbols as in FIG. 1 indicate the same parts. Si substrate 1
A polycrystalline Si layer 9 is provided at a predetermined location of the passivation film (Si02 and/or PSG) 2 provided on the surface of the substrate by vapor deposition and photoetching.

This is to reduce the level difference with the N pad. Next, a PSG film 10 is deposited to a desired thickness by CVD method,
An AI pad 3 is formed on the surface thereof. Thereafter, a PSG protective layer 4 is formed around the AI pad 3.

This PSG protective layer 4 acts as a protective layer for the AI wiring layer. After the formation of this protective layer, a double layer consisting of an NjCr layer 6 and a Pd layer 7 is provided as an under bump metal (UBM) by vapor deposition and photoresist processing. This UB
The center of the M layer is in close contact with the AI pad, and the surrounding area is with the PS.
It is in close contact with the G layer 4. PIQ film 5 is placed on this UBM layer.
The central portion of the UBM layer is exposed by selective etching (eg, by plasma etching). Next, Au is plated on the exposed central part of the UBM layer to form an Au bump 8.
will be established.

The electrode structure shown in FIG. 2 formed in this way consists of one melon layer 6,
Since the periphery of 7 is bonded to the PSG layer 4 instead of the PIQ film 5, the adhesion between the UBM layer and the PSG layer 4 is strong, and the AI pad 3 is prevented from seeping in the etching solution, which is a drawback of the conventional method.
No corrosion phenomenon occurs.

Furthermore, as is clear from FIG. 2, there is no easily broken glass protective film on the AI pad 3, and even if the lead leads are bonded to the Au bumps 8, the glass protective layer 4 will not break. .

FIG. 3 is a diagram illustrating one method for forming an Au plating layer on the UBM layer of FIG. 2.

The figure is a top view of a semiconductor substrate, and numeral 12 indicates an IC or LSI chip area formed on one SJ wafer, around which is a UBM layer before bump formation, numeral 13. All UBM layers 13 are electrically interconnected by wiring layers 14 made of the same metal as the UBM. The wiring layer 14 is PIQ
Although covered by the film 5, the surface of the UBM layer 13 is made of Au.
exposed for plating. An Au plating layer 8 is formed on the UBM layer 13 by connecting one end of the wiring layer 14 to a power source and exposing the Si substrate to an Au plating solution. Finally, by subdividing the substrate into IC or LSI chips, the wiring layer 14 is removed and each bump is electrically isolated. According to such a method, all bumps are formed at once, which is extremely efficient. On top of that, the wiring layer!
Since the wiring layer 4 is covered with the PIQ film 5, the problem that the Au plating layer 8 is partially attached to the surface of the wiring layer 14 does not occur.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an electrode portion of a conventional semiconductor device, FIG. 2 is a sectional view of an electrode portion of the present invention, and FIG. 3 is a top view of a semiconductor wafer for explaining the process of forming Au bumps. . 1...Si substrate, 2...protective (passivation) film, 3...AI pad, 4...PSG
Layer, 5... PIQ film, 6... NjCr thin layer, 7...
Pd thin layer, 8... Au plating layer (bump), 9...
Polycrystalline Si layer, 10...PSG film, 1 2...
...IC chip area, 1 3...UBM layer, 14...metal wiring layer. ※'Figure ※2Figure Chrysanthemum3 figure

Claims (1)

[Claims] 1. An Al pad provided at a predetermined location on a semiconductor substrate via a protective film, a glass layer provided on the semiconductor substrate so as to surround the Al pad without overlapping with the above Al pad, and a glass layer provided on the semiconductor substrate so as to surround the Al pad, and the central portion A thin metal layer that is in close contact with the top surface of the Al pad and has a peripheral portion that is in close contact with the glass layer, and a thin metal layer that exposes the center portion of the thin metal layer and covers the peripheral portion and the top surface of the glass layer. 1. An electrode structure for a semiconductor device, comprising a polyimide resin film formed as described above, and a metal plating layer formed in close contact with the central portion of the exposed thin metal layer.