JPS6052379B2 - Circuit and method for digitally measuring signal level of PCM encoded signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to pulse code modulation (PCM) systems, and more particularly to a new digital circuit for measuring signal levels of PCM signals.

In traditional communication systems such as telephone systems,
When measuring the quality of operation, it is usually necessary to measure the signal level of the transmission line. One method is to apply an analog test signal with a predetermined frequency and characteristics to one of the switching
In this method, the signal is transmitted from the center to the other switching center, where the received signal and the transmitted signal are compared and the resulting signal level is measured. Another method is to use a loopback method, whereby the test signal is looped back to the first switching center where the comparison is made. Many known analog measurement circuits and techniques have been developed to perform this function. Currently developed communication systems use digital coding techniques such as PCM and time division multiplexing.

In these systems, the information appearing on both the switching path and the transmission path is in digital form. but,
There continues to be a need to measure signal levels on these paths. Since known measuring circuits and measuring devices use analog technology, in order to measure the signal level it is necessary to convert the digital signal into an equivalent analog signal. Although this technique is feasible, it tends to be inconvenient, fairly complex, and very expensive because of the need to provide highly accurate digital-to-analog conversion equipment specifically for this purpose. The present invention provides a circuit for direct digital measurement of the signal level of a PCM encoded signal, thereby obviating the need for a digital-to-analog converter for that purpose. Regarding this application, “P
The signal level of the CM signal shall mean the signal level of the analog signal on which the present PCM signal is encoded using the reference analog-to-digital converter. Furthermore, the circuit of the present invention has a relatively small number of off-th
e-shelf) integrated circuits. In accordance with the invention, an analog signal is represented by a predetermined companding law (com
a digital circuit for measuring the level of a PCM signal encoded in accordance with panding1aw), selection means having a position O-n for selecting an integer between 0 and n; n being determined by the selection means; , a sampling circuit for sequentially sampling an input PCM signal 2n times; means for converting each encoded sample into its normalized power representation and further calculating the average power of the samples; and means for calculating an equivalent signal level of the average power. power·
and means for determining a conventional representation of the level.

Further in accordance with the invention, there is also provided a method of measuring the signal level of a PCM signal using the digital measurement circuit of the invention.

The unit DBm is 1 milliwatt (a). Power level table in decibels based on the power of 001 watts)
Used in Shu Yigen.

The decibel is B=1010g10p,-Pwt10
10g10? , the measured power Pl. OOl
The base of the ratio of Watts to the reference power Pr is 10 times the logarithm of 10.

The unit DBmO, as described above, defines an arbitrary zero position. According to international recommendations, PCM representing a 1k pressure signal tone
The zero position of the signal is defined as consisting of the next sample (μm 255 compander code). +97, +11
6, +116, +97, -97, -116, -116,
-97. Preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings.

The block diagram of FIG. 1 illustrates the use of the circuit of the present invention in a PCM telephone switching system.

Digital switching circuitry 1 having an input port for connection to a codec (COdec) containing an analog-to-digital conversion circuit and a digital-to-analog conversion circuit
1 is shown in the diagram, and the codec is analog transmission equipment 1.
Connected to 3.

The digital switching circuitry 11 also has an output port connected to a PCM signal measurement circuit 14 having an output terminal for transmitting the resulting level information to the central processing unit 15. The circuit of FIG. 1 provides an analog-to-analog interface from analog-to-digital and digital-to-analog points in a digital switching system. The use of the digital circuit 14 for measuring PCM signals when measuring subsystem characteristics. represents.

Central processing unit 15 selects the equipment to be tested.

In the case of codec 12 and analog equipment 13, central processing unit 15 causes digital switching circuitry 11 to provide a digital connection or path from codec 12 to PCM signal measurement circuit 14. Since the digital path through switching network 11 passes the PCM signal essentially unchanged, codec 12 is essentially directly connected to measuring circuit 14. In operation, a test signal can be generated in a remote switching network and transmitted along analog facility 13. The signal is converted from analog to digital form in the A/D section of codec 12 and then passed through digital switching circuitry 11 to PCM signal measurement circuit 14, which measures the signal level. The resulting information can be displayed on a visual display or sent to central processing unit 15 for further processing. If the codec 12 is just being tested, the process is as described above, except that the test tone is generated from the digital tone generator 16 and the analog facility 13 is looped back on itself. It is similar to

As is conventional, central processing unit 15 is adapted to provide the necessary control signals to the system circuitry. FIG. 2 is a block diagram of a PCM signal level measurement circuit that can be used in the system of FIG.

Sampling circuit 100 is shown as having an input terminal for receiving a serial PCM input signal. Sampling circuit 100 may consist of commercially available shift registers and output registers suitable for performing serial-to-parallel conversion of data. Its output terminals are often read-only.
It is connected to storage means 101 which may be a memory (ROM).

The storage means 101 receives an input signal W consisting of a total of 8 bits, including a sign bit and 7 bits, and stores a 7-bit mantissa signal A.
. and a 5-bit exponent signal A1. If the PCM code format is of the sign and amplitude type where positive and negative sample points of the same value differ only by 9 sign bits, then the sign-bit combination can be omitted. These signals constitute the square of a linear representation of the instantaneous power of the input signal W. The output terminal of the storage means 101 is 2
It is connected to an accumulator 102 having two input terminals.

Accumulator 102 includes parallel-serial shift register 10
3. Consists of a one-stage synchronous counter 104, a 1-bit adder 105, and a 48-bit shift register 106. Output signal A from storage means 101.

is converted from parallel format to serial format in shift register 103, and shift register 1
The output terminal of 03 is connected to a 1-bit adder 105. The output signal A1 from the storage means is provided to a counter 104 which counts the value of signal A1 and generates an output pulse E which enables shift register 103 to pass signal S1 to one bit adder 105. One-bit adder 105 is responsive to input from the 48-bit shift register and signal S1 from parallel-serial shift register 103 to increment the 48-bit shift register by the value of signal S1.

The serial output signal B1 from the 1-bit adder 105 is also the serial output signal B1 of the accumulator 102.

The 48-bit shift register is the accumulator 10.
Parallel signal B, which is also the parallel output signal of 2.

in response to signal B1 for generating. counter 10
4 is responsive to signal A1 for generating a drive signal after counting a predetermined value corresponding to the value of the index as represented by signal A1.

Parallel-serial shift register 103 converts signal AO from its parallel format to serial format. Serial format output signal S1 is inhibited until drive signal E is provided by counter 104. will be stopped. Parallel serial shift◆
The serial output signal S1 of register 103 is applied to the contents stored in 48-bit shift register 106.
It is provided to an adder 105 which adds bit by bit. The addition of sample points to the accumulated partial sums is 48 bits.
This is done during a 48-bit shift of the shift register. The delay introduced by counter 104 allows new sample points to be added to the partial sum of the 48-bit shift registers of moderate importance. Selection circuit 1
09 determines n which defines the number of samples 2n.

The output signal n is provided to the control circuit 115 for generating the necessary control signals and is further provided to the control circuit 115 to generate the necessary control signals.
7 is provided to an adder circuit 108 that adds a signal to
This gives the counter a value n. counter 107
also responds to signal 8 and provides output signal C1. Shift Register 110 is 48 bits Shift Register 10
It operates as an output buffer for 6.

A second storage means 111 is connected to the output terminal of the shift register 110. Output signal C of storage means 111
. and the output signal C1 of the counter 107 are the multiplication circuit 112.
(described below)). The output terminal of the multiplication circuit 112 is connected to a storage means 113 which functions as a binary code to BCD converter. Storage means 111 and 113 may conveniently be read-only memories. The output sign D. from the multiplication circuit 112. consists of a decimal component DO in 7-bit binary format, one sign bit and an integer component D1 in 7-bit binary code format. The signal is BC in the memory 113.
Converted to D format, in memory 13 each memory location contains a BCD representation of its respective address (7),
Each address corresponds to one possible value of the D signal. The output terminal of one converter may be connected to a visual display 112 or to the central processing unit 15 shown in FIG.

The control circuit 115 receives an external synchronization signal from the central processing unit,
In response to the signal n providing the necessary control signals. answer.

The control circuit has four outputs: two clock signals, clock 1, clock 2, display load and accumulator clear. Clock 2 runs 48 times faster than clock 1 and is used by accumulator 102 for necessary timing. Clock 1 starts the sampling process of sampling circuit 100. Display load means that after 2n samples, the memory 113 outputs the output signal to the display 114.
make it possible to provide The circuit operation in Figure 2 is similar to the circuit operation in Figure 2.
This will be explained along with the functional sequence diagram in the figure.

As previously discussed, the circuit samples the PCM channel in which the PCM signal representing the analog signal is present.

The test signal tone specifying 0 dBm0 consists of the following sequence of code samples of a 1 kHz signal: 197, +116, +116
, +97, -97, -116, -116, -97n is the number of samples from t to 215 (1-3
2768), and the corresponding integration time is . 12
Everything changes from 5n1s.

The value of n is selectable by a selection circuit 109 having positions 0-15. The 8-bit serial sample is processed by sampling circuit 1.
00 is obtained from the serial PCM signal and converted to its parallel form W.

The value of W is converted by storage means 101 into a 12-bit word representing the normalized power such as . Hereden = 7-bit decimal part with a normal range of 64 to 127 A1 = Range of 0-
24 5-bit exponent part K=Constant to facilitate subsequent conversion to DBm 0.37012W=range of PCM code samples 0±8031 Y=operation method of decoded value storage means 101 of PCM code samples W According to this, Y is not considered a signal.

Y<5W is related to the μm25 flood ball extension law. CCnT Recommended G. 7ll, l972, revised 197
6 gives the principle of the μ companding law. The value of the sample W is used as the address in the storage means 101 for determining its corresponding normalized power. In this way there is no need to have hardware to perform the above calculations for each sample, and Y does not exist as a signal. This is possible because the expected values are in a finite range. The accumulated sum of power samples is stored in the accumulator 102 in linear form as described above by a 48-bit shift register 106.

After the powers of the 2n samples determined by the selection circuit 109 are accumulated, the output signal B.

and output signal B1 are available.The total output signal has a resolution of 15 bits, with 8 decimal parts having 9 bits and 8 bits having an exponent part 6 bits. The cumulative sum of power is expressed as follows: Range 8=256-511 The decimal part 8 is converted into 10g2 representation in the second storage means 111.

Integer B1 is modified by decrementing N in counter 107. This is equivalent to dividing the power sum by 2n to give the average power. To facilitate subsequent decoding, a constant 2 is added to the counter 107 to shift the upper range of the exponent.

Therefore, the average power can be expressed as: Furthermore, its binary logarithm can be expressed as: To convert the value of C to DBm, C is a constant 10X10g1 that is very close to 3+ml.

Multiplyed by 2.

Multiplication is performed by multiplication circuit 112. As is known in the art, the implementation of such a multiplier may consist of two parallel adder stages, the first stage being , given here and connecting the signal path C to one of the adders. by connecting the signal path C directly to the input terminals of the second set such that the signal C appears at the input terminals of the second set shifted eight bits to the left.

The output D is obtained by similarly combining C1 and 2C1 in the second stage adder and is given by where D=DO+
It is D1.

The resulting power level number is 0dBm0
with a value between 15 and 135, with the aforementioned constant chosen to yield 128 for (ie the test signal).

Evaluating the result of multiplication 128 in multiplication circuit 112 yields the sign bit. The magnitude of power in DBmO is a 7-bit fractional part D.

and a 7-bit integer D1 as a 14-bit number. Decimal D. The bits and integer D1 bits are stored in storage means 1.
13 to binary coded decimal (BCD).

The values in BCD range from -99.9 to 6.9 and may be displayed on visual display means 114 or further processed as described above.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a portion of a PCM telephone switching system. FIG. 2 is a block diagram of a digital measurement circuit according to the present invention. FIG. 3 is a functional sequence diagram of the circuit of FIG. 2. 11
... Digital switching circuit network, 12... Codec, 14... PCM signal measurement circuit, 15...
Central processing unit.

Claims (1)

[Claims] 1. In a digital circuit for measuring the level of a PCM signal representing an analog signal and coded according to a predetermined companding method, selection means having positions O-n; a sampling circuit for successively sampling the PCM signal 2^n times, where n is determined by the selection means; means for converting each of the samples into a representation of normalized power; A digital circuit comprising: means for calculating the average power of the samples; and means for determining the number of power levels of the average power. 2. said transformation means is a first storage means, each location in said first storage means containing the square of a linear representation of its respective address, each location containing a squared linear representation of said encoded sample; A digital circuit according to claim 1 corresponding to. 3. an accumulator circuit in which the calculation means is responsive to an output signal from the first storage means and a clock signal from a control circuit for generating first and second output signals, the first output signal being a normal of the sample; a parallel data word consisting of the eight most significant bits of an accumulated sum of accumulated sums, the second output signal being a data word representing the position of the most significant bit of the accumulated sum; a second storage means having: each storage location containing the value of lθg2 at its respective address, each address corresponding to a possible one of said first signal; and circuit means for generating a third output signal representative of the index value of the average normalized power of the sample. The digital circuit described in section. 4. The circuit means includes a counter circuit responsive to the second signal to generate the third signal corresponding to the exponent value of the second signal based on the value of the most significant bit of the second output signal. Claim 3, wherein the counter means is also responsive to a signal from the selection means for subtracting a value n from the third signal, so that the third signal represents the average normalized power of the samples. The digital circuit described in section. 5. the accumulator circuit being responsive to the exponent portion of the output signal from the first storage means to provide a drive signal after a predetermined count determined by the exponent portion of the output signal from the first storage means; a parallel-serial shift register suitable for loading the mantissa portion of the output signal from the means and responsive to the drive signal to further provide a serial output signal of its contents: the mantissa portion of the n samples; 4. A digital circuit according to claim 3, comprising a shift register and an adder circuit for determining the cumulative sum of . 6 the means for determining the number of power levels of the average power are a pair of multiplier circuits, one providing the product of the third output signal and a conversion constant, the other providing the product of the output signal from the second storage means and the conversion constant; 5. A digital circuit as claimed in claim 4 providing a product of constants. 7. A digital circuit according to claim 6, which also includes a conversion circuit for combining the output signals from the multiplier circuits and converting them into equivalent binary coded decimal codes, and a visual display for viewing the output signals. . 8. A method for measuring the level of an analog signal represented by a PCM signal representing a predetermined frequency and encoded according to a predetermined companding method, wherein n has a position O-n. P 2^n times in a row as determined
sampling a CM signal, converting each sample to its normalized power representation, calculating the average power of the sample, and converting the value of the average power to an equivalent number of power levels. A method characterized by: 9 Computing the average power of the sample comprises accumulating the sum of the normalized power representations of the sample and adding the normalized power representation of the sample to the sample to obtain the average normalized power of the sample. 9. The method of claim 8, comprising dividing by a number. 10 accumulating the sum of the normalized power representations of the samples serializes the normalized power representations of the samples to obtain a serial format; Claim 9 comprising adding the serial format bit by bit to the partial sum of the previous full serial format representation of the normalized power representation of the 2^n samples to obtain a summation of the representation. The method described in section.