JPS6052572B2 - Wafer for semiconductor devices - Google Patents
Wafer for semiconductor devicesInfo
- Publication number
- JPS6052572B2 JPS6052572B2 JP4251378A JP4251378A JPS6052572B2 JP S6052572 B2 JPS6052572 B2 JP S6052572B2 JP 4251378 A JP4251378 A JP 4251378A JP 4251378 A JP4251378 A JP 4251378A JP S6052572 B2 JPS6052572 B2 JP S6052572B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- crystal layer
- wafer
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Description
【発明の詳細な説明】
本発明は、化合物半導体結晶層を有する半導体装置用ウ
ェーハの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a wafer for a semiconductor device having a compound semiconductor crystal layer.
一般に、化合物半導体装置では、化合物半導体結晶層が
ホモ・エピタキシャル構造をなすウェーハを用いること
が行なわれている。Generally, in compound semiconductor devices, a wafer in which a compound semiconductor crystal layer has a homo-epitaxial structure is used.
そのようなウェーハとしては、化合物半導体単結晶層基
板上にバッファ層、動作層、電極層等となる化合物半導
体単結晶層をそれぞれエピタキシャル成長させた多層構
造のものが用いられている。ところで、前記化合物半導
体単結晶層基板はかなり高価なものであつて、ウェーハ
・コストの大半を占める。Such a wafer has a multilayer structure in which compound semiconductor single crystal layers serving as a buffer layer, an active layer, an electrode layer, etc. are epitaxially grown on a compound semiconductor single crystal layer substrate. By the way, the compound semiconductor single crystal layer substrate is quite expensive and accounts for most of the wafer cost.
また、そのような基板は、例えば、ボート・クロン法や
チョクラルスキー法で製造されるが、シリコン単結晶基
板のように大面積のものが得られにくいことも問題であ
る。従つて、ウェーハ・コストを低減させ、大面積のも
のを得ようとするのであれば、単結晶基板としてシリコ
ン単結晶基板のよう安価で大面積のものを用いれば良い
が、シリコン単結晶基板上に化合物半導体単結晶層を直
接エピタキシャル成長させた場合、シリコンと化合物半
導体との結晶構造の相違或いは格子定数の相違がある為
、結晶欠陥が少なく、鏡面を有し、半導体装置を作り込
める程度に高品質である化合物半導体単結晶層を得るこ
とは困難である。Further, such a substrate is manufactured by, for example, the Bort-Cron method or the Czochralski method, but there is also the problem that it is difficult to obtain a large-area substrate like a silicon single crystal substrate. Therefore, if you want to reduce the wafer cost and obtain a large-area wafer, you can use a cheap and large-area single-crystal substrate such as a silicon single-crystal substrate. When a compound semiconductor single crystal layer is directly grown epitaxially, it has few crystal defects, has a mirror surface, and has a high enough height to fabricate semiconductor devices due to the difference in crystal structure or lattice constant between silicon and compound semiconductor. It is difficult to obtain a compound semiconductor single crystal layer of high quality.
本発明は、安価で大面積のものが得られ易いシリコン単
結晶を基板として用い、その上に高品質の化合物半導体
単結晶層をエピタキシャル成長させたウェーハを得られ
るようにするものであり、以下これを詳細に説明する。The present invention makes it possible to obtain a wafer in which a high-quality compound semiconductor single crystal layer is epitaxially grown on a silicon single crystal, which is inexpensive and easily obtained in a large area, as a substrate. will be explained in detail.
第1図は本発明の基本的実施例を表わす要部側断面図で
ある。図に於いて、1はシリコン単結晶基板、2は酸化
アルミニウム(A12へ即ちサファイア)単結晶層、3
は化合物半導体単結晶層である。FIG. 1 is a side sectional view of a main part showing a basic embodiment of the present invention. In the figure, 1 is a silicon single crystal substrate, 2 is an aluminum oxide (to A12, ie, sapphire) single crystal layer, and 3
is a compound semiconductor single crystal layer.
このウェーハの製造方法は次の通りである。The method for manufacturing this wafer is as follows.
(1)シリコン単結晶基板1上に酸化アルミニウム単結
晶層2を気相成長法を適用して形成する。この気相成長
法を実施するには、通常、次の二つの反応系が考えられ
る。即ち、(イ)アルキル誘導体−C02−H2系、(
口)A1C13−C02−H2系である。しカルながら
、(イ)の反応系は、その取扱いが危険であり、また、
反応温度が低過ぎる欠点がある。(口)の反応系はA1
C13の吸湿性が強いので、成長反応中に水分(H2O
)が混入されて反応初期段階でシリコン単結晶基板1の
表面に二酸化シリコン膜が形成され、酸化アルミニウム
単結晶層2が得られ難い欠点がある。そこで、本発明で
は、反応温度が適当に高く、多数基板への同時成長が可
能であり、また、酸化物質(酸化アルミニウム)の気相
成長ではあるが、シリコン単結晶基板1の表面が二酸化
シリコン膜が形成されないようになし得る反応系として
、A1−HCl−CO2−H2(或いはN2)系を用い
る。(1) An aluminum oxide single crystal layer 2 is formed on a silicon single crystal substrate 1 by applying a vapor phase growth method. To carry out this vapor phase growth method, the following two reaction systems are usually considered. That is, (a) alkyl derivative -C02-H2 system, (
mouth) A1C13-C02-H2 system. However, the reaction system (a) is dangerous to handle, and
The drawback is that the reaction temperature is too low. (mouth) reaction system is A1
Since C13 has strong hygroscopicity, it absorbs water (H2O) during the growth reaction.
) is mixed in, and a silicon dioxide film is formed on the surface of the silicon single crystal substrate 1 at the initial stage of the reaction, making it difficult to obtain the aluminum oxide single crystal layer 2. Therefore, in the present invention, the reaction temperature is appropriately high, simultaneous growth on multiple substrates is possible, and although the oxide substance (aluminum oxide) is grown in a vapor phase, the surface of the silicon single crystal substrate 1 is made of silicon dioxide. As a reaction system that can prevent the formation of a film, an A1-HCl-CO2-H2 (or N2) system is used.
その場合の成長反応式は次の通りてや乙i −ーーこの
場合の成長材料としては、5N(99.999〔%〕)
のに及び4N(99.99〔%〕)のHClを用いる。In that case, the growth reaction formula is as follows. ---The growth material in this case is 5N (99.999 [%])
and 4N (99.99 [%]) HCl.
またシリコン単結晶基板1はカーボ7製支持台上に載置
し、高周波加熱して昇温させる。シリコン単結晶基板の
温度即ちサファイアの結晶成長温度を1100〜120
CfCにした場合、シリコン単結晶基板上に酸化アルミ
ニウム単結晶層(サファイア)2をエピタキシヤル成長
する事が出来る。特に結晶成長温度が1160′Cの時
に良質のγ−サファイアを得る事が出来る。一方上記の
結晶成長温度1100〜1200′C以外の結晶成長温
度領域ではα−サファイア又はαとγ−サファイアの混
晶層が出来る時に1080Cで良質のα−サファイアの
単結晶をエピタキシヤル成長する事が出来る。{2)ア
ルキル化合物の熱分解を利用した気相成長法を適用して
酸化アルミニウム単結晶層2上に化合物半導体単結晶層
3をエピタキシヤル成長させる。Further, the silicon single crystal substrate 1 is placed on a support made of Carbo 7, and heated by high frequency to raise the temperature. The temperature of the silicon single crystal substrate, that is, the crystal growth temperature of sapphire, is set to 1100 to 120.
When CfC is used, an aluminum oxide single crystal layer (sapphire) 2 can be epitaxially grown on a silicon single crystal substrate. Especially when the crystal growth temperature is 1160'C, high quality γ-sapphire can be obtained. On the other hand, in a crystal growth temperature range other than the above-mentioned crystal growth temperature range of 1100 to 1200'C, a single crystal of high quality α-sapphire can be epitaxially grown at 1080C when α-sapphire or a mixed crystal layer of α and γ-sapphire is formed. I can do it. {2) A compound semiconductor single crystal layer 3 is epitaxially grown on the aluminum oxide single crystal layer 2 by applying a vapor phase growth method that utilizes thermal decomposition of an alkyl compound.
化合物半導体がガリウム砒素(GaAs)である場合、
この気相成長法を実施するには、通.常、次の三つの反
応系が亨えられる。When the compound semiconductor is gallium arsenide (GaAs),
To carry out this vapor phase growth method, the following steps are required. Usually, the following three reaction systems can be achieved.
即ち、{イ)トリチルガリウム(TMG: (CH3)
3Ga)とアルシン(AsH3)、(口)トリエチルガ
リウム((C2Yl6)3Ga)とAs鴇、(ハ)ジエ
チルガリウムクロライド((C2H5)2GaC1)と
AsH3である。本発明では、THG−AsH3系を採
用し、酸化アルミニウム単結晶層2を有するシリコン単
結晶基板1を前記工程(1)の場合と同様にして加熱昇
温させる。原料のモル比をXAs2H,/XTMG=1
0−(至)、−成長温度を700〜740〔℃〕として
、高品質且つ鏡面を有するGaAs単結晶を成長させる
ことができた。That is, {a) trityl gallium (TMG: (CH3)
(3Ga) and arsine (AsH3), (1) triethylgallium ((C2Yl6)3Ga) and As oxide, and (3) diethylgallium chloride ((C2H5)2GaC1) and AsH3. In the present invention, the THG-AsH3 system is employed, and the silicon single crystal substrate 1 having the aluminum oxide single crystal layer 2 is heated and heated in the same manner as in the step (1). The molar ratio of raw materials is XAs2H, /XTMG=1
By setting the growth temperature to 700 to 740 [° C.], it was possible to grow a GaAs single crystal of high quality and having a mirror surface.
尚、GaAs単結晶をn型にするには、ドーパントとし
て硫化水素(H2S)又はセレン化水素(H2Se)を
用い、またp型にするには、ドーパントとしてジブチル
ジンク((C4He)2Zn)又はシメメチルジンク(
C2H5)2Znを用いると良い。Note that to make a GaAs single crystal n-type, hydrogen sulfide (H2S) or hydrogen selenide (H2Se) is used as a dopant, and to make it p-type, dibutylzinc ((C4He)2Zn) or sulfide is used as a dopant. Methyl zinc (
It is preferable to use C2H5)2Zn.
前記したように、本発明では、エピタキシヤル成長の酸
化アルミニウム単結晶層2を介在させることに依り、安
価且つ大面積のものを得ることが容易であるシリコン単
結晶基板1の上に高品質の・化合物半導体(例えばGa
As)単結晶層3をエピタキシヤル成長させることがで
きたが、この技術を基礎にして化合物半導体単結晶層を
更に高品質化することが可能である。As described above, in the present invention, by interposing the epitaxially grown aluminum oxide single crystal layer 2, a high-quality silicon substrate 1 is formed on the silicon single crystal substrate 1, which can be easily obtained at low cost and with a large area.・Compound semiconductors (e.g. Ga
As) Although the single crystal layer 3 could be grown epitaxially, it is possible to further improve the quality of the compound semiconductor single crystal layer based on this technique.
即ち、例えば第2図に見られるように、シリコン単結晶
基板1に厚さ0.1〜0.2〔μm〕のγ一A]203
単結晶層2″を成長させ、その上にGaAs単結晶層3
″をエピタキシヤル成長させると、そのGaAs単結晶
層3″の表面は極めて欠陥が少ない、しかも良好な鏡面
にすることができる。That is, for example, as seen in FIG.
A single crystal layer 2″ is grown, and a GaAs single crystal layer 3 is grown on top of it.
By epitaxially growing the GaAs single crystal layer 3'', the surface of the GaAs single crystal layer 3'' can be made to have extremely few defects and a good mirror surface.
一般に酸化アルミニウム単結晶は、α−A]203単結
晶を指しており、このα−Al2O3単結晶基板上へ化
合物半導体の結晶成長は知られている。In general, aluminum oxide single crystal refers to α-A]203 single crystal, and crystal growth of compound semiconductors onto this α-Al2O3 single crystal substrate is known.
このようなα−,Al2O3単結晶板上の化合物半導体
の結晶特性は必ずしも良好なものではなく、例えば、G
a,As基板上へ成長したGaAs結晶に比べてa一A
l2O3単結晶へのGaAs結晶は、移動度が極端に低
い、異常成長が生じやすく鏡面状態の結晶表面が得られ
ない等の問題があつた。しかし、γ−Al2O3単結晶
基板への化合物半導体結晶は半導体装置の製造に供する
のに充分な良質の結晶である。The crystal properties of compound semiconductors on such α-,Al2O3 single crystal plates are not necessarily good; for example, G
a-A compared to a GaAs crystal grown on an As substrate.
GaAs crystals formed into 12O3 single crystals have problems such as extremely low mobility, a tendency to abnormal growth, and the inability to obtain mirror-like crystal surfaces. However, the compound semiconductor crystal on the γ-Al2O3 single crystal substrate is of sufficient quality to be used in the manufacture of semiconductor devices.
酸化アルミニウム単結晶層上にGaA>単結晶層をエピ
タキシヤル成長させる場合、酸化アルミニウムがα−A
l2O3である場合よりもγ−Al2O3である方が好
結果が得られる理由として、例えば、ビル●ロツクやピ
ラミツド状の異状成長、クラツク等が殆んどなく、鏡面
を有し、厚さが均一であるGaAs単結晶層を得ること
ができる。When epitaxially growing a GaA>single crystal layer on an aluminum oxide single crystal layer, aluminum oxide
The reason why γ-Al2O3 gives better results than l2O3 is that, for example, there are almost no building blocks, pyramid-like abnormal growths, cracks, etc., it has a mirror surface, and the thickness is uniform. A GaAs single crystal layer can be obtained.
従つて、本発明に依る成長を行なうには、シリコン単結
晶基板1上にγ−Al2O3単結晶層2″をエピタキシ
ヤル成長させて、Ga,Asの成長を行なうと良い。前
記のように酸化アルミニウム単結晶層上にGaA>単結
晶層を成長させる場合、酸化アルミニウムがα−Al2
O3であるよりもγ−Al2O3である方が異常成長を
生じ難い理由として、α−A]203が六方晶構造であ
るのに対し、γ−AI2O3はGa,Asと同じく立方
晶スピネル構造であるため、格子不整合に依る欠陥発生
が少ないものと考えられる。尚、第2図実施例に於て、
シリコン単結晶基板1として、その結晶面が低指数面よ
り数度、例えば2〜5〔度〕ずれたものを使用すること
に依り、GaAs単結晶層3″に発生する異常成長の割
合は更に急激に低下する。さて、例えば、GaAs−M
ES−FETのようなプレーナ構造の半導体装置を製造
する場合、基板としては、絶縁性或いは半絶縁性のもの
を使用する。Therefore, in order to perform the growth according to the present invention, it is preferable to epitaxially grow a γ-Al2O3 single crystal layer 2'' on the silicon single crystal substrate 1, and then grow Ga and As. When growing a GaA>single crystal layer on an aluminum single crystal layer, aluminum oxide is α-Al2
The reason why abnormal growth is less likely to occur with γ-Al2O3 than with O3 is that α-A]203 has a hexagonal crystal structure, whereas γ-AI2O3 has a cubic spinel structure like Ga and As. Therefore, it is thought that defects caused by lattice mismatch are less likely to occur. In addition, in the example shown in FIG.
By using a silicon single crystal substrate 1 whose crystal plane is shifted by several degrees, for example 2 to 5 degrees, from the low index plane, the rate of abnormal growth occurring in the GaAs single crystal layer 3'' can be further reduced. It decreases rapidly.Now, for example, GaAs-M
When manufacturing a semiconductor device with a planar structure such as an ES-FET, an insulating or semi-insulating substrate is used.
従つて、第1図或いは第2図に見られるウエーハを用い
ることができるが、より良い効果を得る為には第3図に
見られるよ構造のウエーハを使用すると良い。第3図に
於いて、1はシリコン単結晶基板、2は酸化アルミニウ
ム単結晶層、4は半絶縁性GaAs単結晶層(バツフア
層)、5はn型GaAs単結晶層(動作層)、6はn+
型GaAs(或いはGaAlAs)単結晶層(電極層)
てある。Therefore, the wafer shown in FIG. 1 or 2 can be used, but in order to obtain better effects, it is better to use a wafer having the structure shown in FIG. 3. In FIG. 3, 1 is a silicon single-crystal substrate, 2 is an aluminum oxide single-crystal layer, 4 is a semi-insulating GaAs single-crystal layer (buffer layer), 5 is an n-type GaAs single-crystal layer (active layer), 6 is n+
Type GaAs (or GaAlAs) single crystal layer (electrode layer)
There is.
前記バツフア層である半絶縁恒ρAAl,単結晶層4は
、結晶中にクロム(Cr)、鉄(Fe)、マンガン(M
Tl)、酸素(0)等、半導体中て深い不純物準位を作
る不純物をドーピングし、エピタキシヤル成長に依り得
ることができる。動作層であるNSρAAs単結晶層5
上には電極層であるn+型GaAs単結晶層6を成長す
るか、或いは、p−n接合型であればGaAlAsを成
長させるものである。The buffer layer, semi-insulating constant ρAAl, single crystal layer 4 contains chromium (Cr), iron (Fe), manganese (M
It is possible to perform epitaxial growth by doping with an impurity that creates a deep impurity level in the semiconductor, such as Tl) or oxygen (0). NSρAAs single crystal layer 5 which is an active layer
An n+ type GaAs single crystal layer 6 serving as an electrode layer is grown thereon, or if it is a pn junction type, GaAlAs is grown.
このようにして得られたウエーハを用いて製造されたM
ES−FETは出力、利得、胛、Fma8全ての点に於
いて、従来のウエーハ、即ち、半絶縁性GaAs基板上
に動作層をホモ・エピタキシヤル成長させた構成のもの
を用いたMES−FETと静的にも動的にも類似する特
性を得ることができた。M manufactured using the wafer thus obtained
The ES-FET is a MES-FET that uses a structure in which the active layer is grown homo-epitaxially on a conventional wafer, that is, a semi-insulating GaAs substrate, in terms of output, gain, width, and Fma8. We were able to obtain similar characteristics both statically and dynamically.
前記説明はMES−FETを製造するのに好適なウエー
ハに関するものであるが、化合物半導体を用いる装置の
重要なものとしてガン・ダイオード、バラクタ、ミキサ
・ダイオード等のマイクロ波半導体装置があり、このよ
うな装置をハイブリツド化する場合、第4図に見られる
ようなウエーハを用いると良い。即ち、図示のウエーハ
では、酸化アルミニウム単結晶層2の上に電極層として
n+型GaAs単結晶層7を成長させてあり、その上に
動作層であるNyfJaAs単結晶層5を成長させれば
プレーナ型半導体装置の製造に用いることができる。尚
、n+型GaAs単結晶層7に於ける不純物濃度は、通
常、5×1018〔d−3〕以上とする。以上の説明で
判るように、本発明に依れば、GaAs単結晶基板より
安価であり、且つ、大面積のものが容易に得られるシリ
コン単結晶基板上に酸化アルミニウム単結晶層を介して
良質の化合物半導体単結晶層を形成したウエーハが得ら
れ、このウエーハを用いることに依り、化合物半導体装
・置は著しく安価に製造できることになる。Although the above description relates to a wafer suitable for manufacturing MES-FETs, important devices using compound semiconductors include microwave semiconductor devices such as Gunn diodes, varactors, and mixer diodes. When hybridizing devices, it is preferable to use a wafer as shown in FIG. That is, in the illustrated wafer, an n+ type GaAs single crystal layer 7 is grown as an electrode layer on an aluminum oxide single crystal layer 2, and a planar NyfJaAs single crystal layer 5 is grown as an active layer thereon. It can be used for manufacturing type semiconductor devices. Note that the impurity concentration in the n+ type GaAs single crystal layer 7 is normally set to 5×10 18 [d−3] or more. As can be seen from the above description, according to the present invention, a high-quality aluminum oxide single crystal layer is formed on a silicon single crystal substrate, which is cheaper than a GaAs single crystal substrate and can easily be obtained with a large area. A wafer having a compound semiconductor single crystal layer formed thereon is obtained, and by using this wafer, compound semiconductor devices can be manufactured at extremely low cost.
第1図乃至第4図は本発明に依るそれぞれ異なる実施の
要部側断面図である。
図に於いて、1はシリコン単結晶基板、2は酸)化アル
ミニウム単結晶層、3は化合物半導体単結晶層である。1 to 4 are side sectional views of main parts of different embodiments according to the present invention. In the figure, 1 is a silicon single crystal substrate, 2 is an aluminum oxide single crystal layer, and 3 is a compound semiconductor single crystal layer.
Claims (1)
しめられたγ型酸化アルミニウム(γ−Al_2O_3
)単結晶層及び化合物半導体単結晶層を有してなること
を特徴とする半導体装置用ウェーハ。1 γ-type aluminum oxide (γ-Al_2O_3) grown epitaxially on a silicon single crystal substrate
) A wafer for a semiconductor device comprising a single crystal layer and a compound semiconductor single crystal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4251378A JPS6052572B2 (en) | 1978-04-10 | 1978-04-10 | Wafer for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4251378A JPS6052572B2 (en) | 1978-04-10 | 1978-04-10 | Wafer for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54134554A JPS54134554A (en) | 1979-10-19 |
| JPS6052572B2 true JPS6052572B2 (en) | 1985-11-20 |
Family
ID=12638143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4251378A Expired JPS6052572B2 (en) | 1978-04-10 | 1978-04-10 | Wafer for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052572B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0648713B2 (en) * | 1985-01-10 | 1994-06-22 | 株式会社日立製作所 | Multi-layer semiconductor device |
| US6583034B2 (en) | 2000-11-22 | 2003-06-24 | Motorola, Inc. | Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure |
-
1978
- 1978-04-10 JP JP4251378A patent/JPS6052572B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54134554A (en) | 1979-10-19 |
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