JPS6052599B2 - Photosensitive oscillation element - Google Patents

Description

Detailed Description of the Invention The present invention provides an n-type semiconductor layer 2 on the upper surface of a p-type semiconductor layer 1, forms an n-type high concentration impurity layer 3 in this n-type semiconductor layer 2, and also forms an n-type semiconductor layer 2 on the upper surface of a p-type semiconductor layer 1. A p-type impurity layer 4 is formed in a part of the upper part of the layer 2, an n-type impurity layer 5 is provided on this p-type impurity layer 4, and another n-type impurity layer 6 is provided in another part of the upper part of the n-type semiconductor layer 2. The present invention relates to a photosensitive oscillation device characterized by comprising:

As shown in FIG. 1, the conventional optical oscillation device includes an n-type semiconductor layer 2 provided on the upper surface of a p-type semiconductor layer 1, a p-type impurity layer 4 formed in a part of the upper part of the n-type semiconductor layer 2, and An n-type impurity layer 5 is provided on the n-type impurity layer 4, and another n-type impurity layer 6 is formed on the n-type impurity layer 4.
As shown in the figure, a DC power source Va and a load resistor RL are connected between electrodes E and C provided on both n-type impurity layers 5 and 6, respectively. When an oscillation circuit is constructed by connecting series circuits of , the oscillation pulse electric current flowing through the circuit of the n-type impurity layer 6, the n-type semiconductor layer 2, and the p-type impurity layer 4 is due to the lateral resistance of the n-type semiconductor layer 2. However, there was an omission in that the oscillation pulse current 1 could not be increased because this lateral resistance was large. The present invention has been made in view of the above drawbacks, and its object is to provide a photoreceptive oscillation element that can extract a large oscillation pulse current.

The present invention will be explained below with reference to Examples. FIG. 1 shows a circuit configuration diagram of one embodiment. Using a p-type semiconductor layer 1 as a substrate, an n-type semiconductor layer 2 is provided on the p-type semiconductor layer 1 by an epitaxial growth layer. An n-type high concentration impurity layer 3 is partially formed as a buried layer, and then the n-type semiconductor layer 2 is epitaxially grown to complete the n-type semiconductor layer 2. Further, a p-type impurity layer 4 is provided in a part of the n-type semiconductor layer 2, a highly concentrated n-type impurity layer 5 is provided on the p-type impurity layer 4, and an ohmitry electrode is provided in another part of the n-type semiconductor layer 2. For this purpose, an n-type impurity layer 6 is provided, and electrodes E and C are formed on both n-type impurity layers 5 and 6. Thus, an oscillation circuit is constructed by connecting a load resistor RL and a series circuit with a DC power source Va between both electrodes C and E, and when the light L is now irradiated onto the top surface of the element, the n-type semiconductor layer 2, Pairs of electrons and holes are generated in the n-type high-concentration impurity layer 3, and the holes, which are minority carriers, flow into the p-type semiconductor layer 1 by diffusion.

The potential of the p-type semiconductor layer 1 increases due to the inflow of holes, and the potential of the p-type semiconductor layer 1 increases until it becomes equal to or slightly higher than that of the n-type impurity layer 6. On the other hand, due to light irradiation, a photocurrent 1 is flowing through the n-type semiconductor layer 2 and the n-type high concentration impurity layer 3. Due to the voltage drop, near the 5th point of junction J2,
The p-type semiconductor layer 1 has a positive potential, and the n-type high concentration impurity layer 3 has a negative potential, and the p-type impurity layer 4 is also irradiated with the light L. Therefore, the p-type semiconductor layer 1, the n-type semiconductor layer 2, In the thyristor structure of the p-type impurity layer 4 and the n-type impurity layer 5, the junction J
1 becomes conductive, and current flows through the element. In this case, holes are injected from the p-type semiconductor layer 1 into the n-type high concentration impurity layer 3, and electrons from the n-type impurity layer 5 flow into the p-type semiconductor layer 1, so that the potential of the p-type semiconductor layer 1 rapidly increases. Finally, the potential of the p-type semiconductor layer 1 becomes lower than that of the n-type high concentration impurity layer 3, and the junction J2 becomes reverse biased. The current flowing through the structure of impurity layer 4 and n-type impurity layer 5 is stopped. However, junction J1
Junction J1 remains conductive due to excess carriers in the p-type impurity layer 4 and n-type semiconductor layer 2 near the n-type semiconductor layer 2.
The sum of the current x1 flowing through the n-type high concentration impurity layer 3 and the current flowing through the n-type high concentration impurity layer 3 flows as a pulse current. When the excess carriers near this junction J1 disappear due to an electric field or recombination, the element becomes completely non-conductive and no current flows.
Holes generated in the n-type semiconductor layer 2 and n-type high concentration impurity layer 3 by light irradiation flow into the p-type impurity layer 4, and when the potential of this p-type impurity layer 4 becomes high again, the element becomes conductive. This conduction and non-conduction are repeated to maintain oscillation.
In addition, in the case of strong light L, the potential rise of the p-type semiconductor layer 1 becomes faster and the non-conducting period becomes shorter, resulting in a higher oscillation frequency.If the light L is weaker, the non-conducting period becomes longer and the oscillation frequency increases. becomes lower. FIG. 3 shows a circuit configuration diagram of another embodiment of the present invention, in which an n-type high-concentration impurity layer 3 is embedded in the n-type semiconductor layer 2 to increase the withstand voltage of the junction J2. There is.

Although the n-type semiconductor layer 2 is provided on the top surface of the p-type semiconductor layer 1 in the above embodiment, it is of course possible to provide a p-type semiconductor layer on the top surface of the n-type semiconductor layer. 4 is provided, and an n-type impurity layer 5 is provided on this p-type impurity layer 4, but an n-type impurity layer is provided in the n-type semiconductor layer 2, and a p-type impurity layer is provided on this n-type impurity layer. Good too.

In the present invention, since the n-type high-concentration impurity layer is provided in the n-type semiconductor layer, the current flowing through this n-type high-concentration impurity layer becomes extremely large due to the extremely small resistance of the n-type high-concentration impurity layer. This has the effect that a large oscillation pulse current can be extracted, which is determined by the sum of the current flowing through the n-type semiconductor layer and the above-mentioned current flowing through the n-type high concentration impurity layer.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional example, FIG. 2 is a circuit configuration diagram of one embodiment of the present invention, and FIG. 3 is a circuit diagram of another embodiment of the present invention. An n-type semiconductor layer, 3 is an n-type high concentration impurity layer, 4 is a p-type impurity layer, and 5 and 6 are n-type impurity layers.

Claims (1)

[Claims] 1 An n-type semiconductor layer is provided on the top surface of the p-type semiconductor layer, and this n-type semiconductor layer is provided on the top surface of the p-type semiconductor layer.
forming an n-type high concentration impurity layer in the n-type semiconductor layer, and forming a p-type impurity layer in a part of the upper part of the n-type semiconductor layer;
A photosensitive oscillation device characterized in that an n-type impurity layer is provided on the p-type impurity layer, and another n-type impurity layer is provided in other parts above the n-type semiconductor layer.