JPS6052652B2 - automatic speed equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic speed adjusting device that matches the output frequency of a generator to the output frequency of a power system.

This automatic speed adjusting device is used when starting a generator and connecting it in parallel to the power grid. FIG. 1 is a block diagram showing an example of a conventional device.

In the figure, 1 is a three-phase alternating current generator, 2 is a disconnector for connecting the generator 1 in parallel to the grid, 3, 4, 5 are potential transformers (hereinafter abbreviated as PT), . Reference numerals 6, 7, and 8 are auxiliary transformers having a plurality of secondary windings that generate the same voltage. 9
, 10, 11 are full-wave rectifiers composed of diode bridges, 12, 13, 14 are smoothing capacitors, 1
5, 16, and 17 are resistors, and 18 is a positive bias voltage! 19, 20, 21 are reverse current blocking diodes, 22, 23, 24 are input resistors, 25 to 34 are NOR gates (NOR gate).The display method of NOR gate as shown in Fig. 1 will be explained later. In Section 2, we will explain about Figure 2.

35 and 36 are input resistors, 37 and 38 are bias resistors,
39, 40 are power transistors, 41, 42 are surge killer capacitors, 43, 4
4 is an arc extinguishing diode, 45 is a relay 15L that controls to lower the governor motor (not shown) of the starter generator that drives the generator 1, and 15R is a relay 15R that controls the governor motor to be raised. 47 and 48 are Noah gates;
is a reverse current blocking diode, 50 and 51 are variable resistors, and 5
2 is a capacitor, 53 is a Zener diode, 54, 55
56 is a resistor, 57 is a capacitor, 58 is a resistor, 59 is a pulse interval control circuit, and 60 and 61 are reverse current blocking diodes.

Also, Figure 2 is an explanatory diagram explaining the display method of Noah Gate,
FIG. 2a is a connection diagram showing an example of a NOR gate, and FIG. 2b is a symbol representing a circuit corresponding to FIG. 2a.

101, 102, 103 are the input resistances of the NOR gate, 10
4 is a bias resistor, 105j is a transistor, and 106 is a collector resistor.

FIG. 2c is a symbol representing a NOR gate when there is no input resistance. A NOR gate generally has multiple input terminals, but if only one input terminal is used and is represented as shown in Figure 2c, an inverter (Inv
erter). Next, the operation of the circuit shown in FIG. 1 will be explained.

FIG. 3 is a waveform diagram showing the output waveforms of the full-wave rectifiers 9, 10, and 11 in FIG.
shows the output voltage of the rectifier 10, and FIG. 3c shows the output voltage of the rectifier 11. The voltage between the RS phases (in this specification, the first phase is generally referred to as, for example, the RS phase) voltage of the grid is detected by the PT3 and the auxiliary transformer 6, and the RS phase voltage of the generator 1 is P
The composite value of both voltages detected by T4 and the auxiliary transformer 7, that is, the AC voltage whose amplitude changes at the beat frequency of the difference in frequency between the two voltages, is input to the rectifier 9, and the pulsating voltage at the beat frequency is converted into a full wave. It is rectified and output as a negative polarity voltage shown in FIG. 3a. The AC component is smoothed by a capacitor 12. This rectified output is of negative polarity and bias setter 1
8 is added to the positive polarity bias voltage given by 8, and only the portion below the dotted line in FIG. Rectifier 1
0, the voltage between the RS phases of the system from the auxiliary transformers 6 and 8 and the voltage between the ST phases of the generator 1 (generally in this specification, the second phase phase is the composite value of the voltage (even if it is referred to as the ST phase phase). is input to the rectifier 11 from the auxiliary transformers 6, 7, and 8 to the RS interphase voltage of the grid and the TR phase voltage of the generator 1 (in this specification, the third phase interval is generally referred to as the TR phase voltage, for example). In addition, in the example shown in Fig. 1, the voltage between the swimming phases is the auxiliary transformer 7,
8, the RS inter-phase voltage is obtained by adding the ST inter-phase voltage. ) Since the composite value of the voltages is input, the third
The waveforms shown in Figures B and c are output. In this case, if the frequency of the output voltage of the generator is f1 and the frequency of the grid voltage is F2, the frequency Δf of the pulsating voltage shown in FIG. 3 is Δf=1f1
-F2l, and it is well known that when f1>F2, the phase of each pulsating voltage shown in FIG. This is where I am.

In other words, if f1>F2, the pulse voltage passes through the diode 19 and then the diode 20, but if f1<F2, the pulse voltage passes through the diode 19 and then the pulse voltage passes through the diode 21. pass.
In Figure 1, Noah gates 25, 26, Noah gate 27
, 28, Noah Gate 29, 30 and Noah Gate 54, 5
Each pair of Noah gates of 5 is a flip-flop (Fllp
flOp).

When a positive pulse is applied to the NOR gate 25 through the resistor 22, its output becomes "0", so the NOR gate 2
6 becomes 1, and this state is maintained until a positive pulse is applied to the input of NOR gate 26. This state will be temporarily referred to as the set state of the flip-flop. Noah Gate 28 and 29 have Noah Gate 2.
Since the output of 5 is input, the flip-flops of NOR gates 27 and 28 and the flip-flops of NOR gates 29 and 30 will not be set unless the flip-flops of NOR gates 25 and 26 are set. Also, the output of NOR gate 28 is input to NOR gate 29, and the output of NOR gate 29 is input to NOR gate 28, so when the flip-flops of NOR gates 27 and 28 are set, the flip-flops of NOR gates 29 and 30 are not set. Noah Gate 29,
When the flip-flops 30 are set, the flip-flops of the NOR gates 27 and 28 are not set. Therefore, when f1>F2, the flip-flops of Noah gates 25 and 26 are set, then the flip-flops of Noah gates 27 and 28 are set, and the flip-flops of Noah gates 29 and 30 are not set, and when f1<F2 When , Noah Gate 25,2
6 flip-flop is set, then Noah gate 2
Flip-flops 9 and 30 are set, and flip-flops of NOR gates 27 and 28 are not set. When the flip-flops of Noah gates 27 and 28 are set, relays 15L and 45 are energized and the governor motor is rotated in the downward direction to lower f1, and when the flip-flops of Noah gates 29 and 30 are set, relay 15R46 is energized. Rotate the governor motor in the upward direction to raise f1 and f1=
Make it F2. On the other hand, in the NOR gate 47, all inputs become "゜0゛" after the pulse shown in FIG. 3a is output until the next pulse shown in FIG. The repetition period T of the pulse is T=l/Δ
f1Δf=1f1−F2! Therefore, the time T1 during which the output of the NOR gate 47 is ゜゜1゛ is T1=1
20T/360=1/3Δf. Capacitor 52 is charged via diode 49 and resistor 50 during time T1. FIG. 4 is a waveform diagram showing the voltage progression of this capacitor 52, where the horizontal axis shows time t, and if the starting point of charging via the resistor 50 is t=0, the ending point is t=T1.
However, when Δf is large, T1 is small, for example at the point t=Tll in FIG. 4, and when Δf is small, T1 is large, for example at the point Tl2. At the point t=T1, the output voltage of the NOR gate 47 becomes "0", the output voltage of the NOR gate 33 or 34 becomes "1", and the capacitor 52 becomes the resistor 51.
is charged via. When the J voltage of the capacitor 52 reaches the Zener voltage Ez of the Zener diode 53, a positive pulse is applied to the NOR gate 54 to set the flip-flops of the NOR gates 54 and 55. The output of the NOR gate 55 is input to the NOR gates 33, 34, 47, and 48, and while the output of the NOR gate 557 is "1", the NOR gate 33,
The outputs of 34, 47, and 48 are kept at ゜゜0゛. As a result, relays 15L, 45 (or relay 15R46) become inoperable. Therefore, if the frequency difference Δf is large, T1 becomes Tl
A small relay 15L. The time TOl in which relays 15L and 45 are operated is long, and when Δf is small, T1 becomes large as Tl2, and the time T in which relays 15L and 45 are operated is long.
C2 is short.

FIG. 5 is a graph showing the relationship between Δf and the governor motor drive time (ie, relay operation time) TO, and shows the cases where R=large, R=medium, and R=small, using the resistance value R of the resistor 51 as a parameter. The output of the NAND gate 54 is input to the pulse interval control circuit 59, and after a certain period of time, a pulse of "゜1゛" is outputted and input to the NAND gates 26, 28, 29, and 55 to reset the flip-flops constituted by these NAND gates.After reset First, the flip-flops of NAND gates 25 and 26 are set, and the operation described above is repeated.Diodes 49, 60, and 61 are used to prevent backflow.
As described above, when f1>F2, relay 15L45
is operated to lower f1, and when f1<F2, the relay 15R46 is operated to increase f1, and 1f1
If -F2l=Δf is large, control is performed to increase the amount of decrease or increase in f1 by increasing the time during which these relays are operated so that f1=F2. The conventional automatic speed adjusting device is configured as described above, and the tolerance of the resistors 50 and 51 is about ±5%, the tolerance of the capacitance of the capacitor 52 is about ±10%, and the zener diode 53 has a tolerance of about ±5%. The voltage E2 also has an error of about 10%, and as a result of these factors, there is considerable variation in the characteristics of the governor drive time shown in Figure 5.In addition to adjusting each time, we also collected test data and set the resistor 50% based on this test data. , 51 must be set, and the value once adjusted may change due to changes in temperature, changes over time, etc.

This invention was made to eliminate the drawbacks of the conventional device as described above, and in this invention, the governor motor drive time control circuit is digitized and adjusted. The purpose is to eliminate the need for maintenance. Embodiments of the invention will be described below with reference to the drawings.

FIG. 6 is a block diagram showing one embodiment of the present invention.
In the figures, 1 to 5, 7 to 8, 35 to 46 indicate the same or corresponding parts as the same reference numerals in FIG. 65 is an auxiliary transformer,
66 to 69 are rectangular wave generation circuits which input voltages between the RS phases of the grid, between the RS phases of the generator 1, between the ST phases, and between the TR phases and convert them into rectangular waves.
While the terminal marked with an x in Figure 6 on the secondary side of 5, 7, and 8 is at high potential Z, the voltage at the ゜゛H level of the square wave is applied to the terminal marked with an x. When is at a low potential, it outputs a rectangular wave "゜L" level voltage. 70 to 72 are exclusive OR gates, and the above ゜"H" level voltage is set as logic ゜"1" and 64V9L/
/<, L/ voltage is set as logic 66099 and its exclusive OR is output.

In the embodiment shown in FIG.
0, 71, 72 as referred to in this specification as the first, second,
A third phase difference detection circuit is configured. Pulse width detection circuits 73 to 75 output pulses when the pulse widths of the output pulses of the exclusive OR gates 70 to 72 exceed a predetermined value.

7) 6-86 are NANDgate, 8
7 to 91 are inverters, 92 and 93 are resistors, 94 and 95
is a capacitor, 96 and 97 are Schmitt circuits, 98-1
01 is NAND gate, 102 is up counter, 103
is a read-only memory (hereinafter abbreviated as ROM).

Often PrOgrammableROM or P
104 is a presettable down counter to which the output of the ROM1O3 is preset. 105 and 106 are NAND gates, 108 is a pulse interval control circuit, 109 is a crystal oscillation circuit, 110, 111,
112 are frequency dividing circuits.

FIG. 7 is a waveform diagram showing the voltage waveform of a specific part in FIG. 6, where a is the input voltage of PT3, b is the input voltage of PT4,
c is the output voltage of the exclusive OR gate 70, d is the output voltage of the pulse width detection circuit 73, e is the output voltage of the exclusive OR gate 71, and f is the pulse width detection circuit 7
4, g is the output voltage of the exclusive OR gate 72, and h is the output voltage of the pulse width detection circuit 75.

FIG. 8 is a waveform diagram showing voltage waveforms in other specific parts of FIG. is the output voltage of the NAND gate 98, e is the output voltage of the inverter 90, f is the terminal voltage of the capacitor 96, g is the output voltage of the Schmitt circuit 97, and h is the output voltage of the NAND gate 99. The operation of the circuit shown in FIG. 6 will be explained below using FIGS. 7 and 8.

As explained in the circuit of Fig. 1, when f1>F2, or f1 - F2, the phase difference between the phase-to-phase voltage of the grid and the phase-to-phase voltage of generator 1 is Δf as shown in Fig. 7A, b. =Ifl-
The outputs of the exclusive OR gates 70, 71, and 72 change as shown in FIG. 7C, E, and G, respectively. The dashed lines in FIG. 7C, e, and g show the progression of changes in the pulse width of each output pulse. When this pulse width exceeds a certain value, the pulse width detection circuits 73, 74, and 75 detect negative polarity pulses. The outputs of the circuits 73, 74, and 75 are as shown in FIG. 7D, f, and h, respectively. Nand Gate 76, 77
, NAND gates 78, 79, and NAND gates 80, 81 constitute flip-flops, which will be referred to as first, second, and third flip-flops, respectively, in this specification.

When the negative polarity pulse shown in FIG. 7d, that is, the pulse of "0" is applied from the pulse width detection circuit 73 to the NAND gate 76, the output of the NAND gate 76 becomes "1" and the output of the NAND gate JMoV becomes "440". This state is maintained until a subsequent pulse of negative polarity is applied to NAND gates JMOV.This state is temporarily referred to as the set state of the flip-flop.NAND gates 79 and 81 have 76
Since the output of is input, the second flip-flop 78
, 79 and the third flip-flops 80, 81 are not set unless the first flip-flops 76, 77 are set. Furthermore, the output of the NAND gate 79 is input to the NAND gate 81, and the output of the NAND gate 81 is input to the NAND games 1 and 79, so when the second flip-flops 78 and 79 are set, the third flip-flop 80, 81 are never set, and the third flip-flop 80, 8
While the flag is set to 1, the second flip-flops 78 and 79 are never set. That is, the above-mentioned mutual lock circuit is provided between the second flip-flops 78, 79 and the third flip-flops 80, 81. When the first flip-flops 76 and 77 are set and then the second flip-flops 78 and 79 are set, the transistor 39 is turned on via the NAND gates 82 and 84 and the inverter 87, and the relay 15L. 45 to lower f1.

Further, when the third flip-flops 80, 81 are set after the first flip-flops 76, 77 are set, the transistor 40 is turned on via the NAND gates 83, 85 and the inverter 88, and the relay 15R4 is turned on.
6 to raise f1. The output of the NAND gate 86 is logical after the first flip-flops 76, 77 are set, and then the second flip-flops 78, 79 are logic until the third flip-flops 80, 81 are set.
Therefore, the terminal voltage of the capacitor 94, the output voltage of the Schmitt circuit 96, and the output voltage of the NAND gate 98 have the waveforms shown in FIG. 8B, c, and d. Then, the count value of the up counter 102 is reset to zero by the pulse shown in FIG. 8d.

Further, the output of the inverter 90 is as shown in FIG.
0 and the up counter 102 is counted up. The frequency of the pulses input to the up counter 102 is referred to as a second frequency in this specification. The count value of the up counter 102 is input to the ROMIO3 and the ROMIO
3 outputs a predetermined numerical value as a function of the input and inputs it to the parallel input terminal of the down counter 104. The terminal voltage of the capacitor 95, the output voltage of the Schmitt circuit 97, and the output voltage of the NAND gate 99 are as shown in FIG. 8F, g, and h, respectively, and at the time of the pulse in FIG.
The output of is preset to the down counter 104. While the output of the NAND gate 96 (FIG. 8a) is "°1", the output pulse of the frequency dividing circuit 112 is
It is added to the down counter 104 from 1 to count down. In this specification, this down counter 1
The frequency of the pulse input to 04 is called a first frequency. When the count value of the down counter 104 becomes zero, an overflow pulse (that is, a carry pulse) is output, which sets the flip-flop gates (referred to as the fourth flip-flop in this specification) of the NAND gates 105 and 106, and outputs the NAND gates 82 and 83. After a predetermined time period applied to the pulse interval control circuit, the first, second, third, and fourth flip-flops are reset, and then a pulse is output from the pulse width detection circuit 73. When this pulse is output, the above operation is repeated. The operations of the up counter 102, ROMIO3, and down counter 104 will be explained below using numerical examples. The output frequency of the crystal oscillation circuit 109 is set to 1 MHz, and the output frequency of the frequency dividing circuit 111 (i.e., the second frequency) is set to 1 MHz/214.
shall be. In other words, the period of the pulse input to the up counter 102 is 10-6 x 214 = 0.016384 (Se
c), and the count value of the up counter 102 indicates T,=±, and FIG. 9 shows the 3Δf up counter 10.
2 is a correspondence diagram showing functions of T1 and Δf,
The count value of this up counter 102 becomes the input to the ROMIO3.

FIG. 10 is a correspondence diagram showing the relationship between the input and output of the ROMIO3. In other words, if the input value is large, T1 is large.
Since Δf indicates a small value, the larger the input numerical value is, the smaller the output numerical value is, so that control for a short period of time corresponding to the small Δf is provided. The output frequency (i.e., the first frequency) of the frequency dividing circuit 112 is set to 1 MHz/217, and the period of the pulse input to the down counter 104 is set to 10.
-6×217=0.131072(Sec) then R
The output value of OMlO3, that is, the value preset in the down counter 104 and the relay 15L, 45 or relay 15
Time limit for R46 to be energized, that is, time limit T for driving the governor motor. FIG. 11 shows the relationship between FIG. 12 is a graph showing the relationship between Δf and relay energization (governor motor drive) time limit Tc, and the solid line shows the case based on the above-mentioned numerical example.

The relationship between Δf and the relay energization time can be changed by changing the functional relationship between the input and output of the ROMIO3 and by changing the ratio between the first frequency and the second frequency.
For example, the output frequency of the frequency dividing circuit 111 can be changed by switching the output stages of the frequency dividing circuits 110 and 111. 1MHz/215
, 1 MHz/216, it is easy to understand that the characteristics shown by the dotted line and the dashed-dotted line in FIG. 12 are obtained, respectively. One input 1 of the NAND gates 98 and 99 presets the counters 102 and 104 at the moment the power is turned on. This is a circuit to prevent malfunction.

As described above, relays 15L, 45, and relay 15R
46 to control the governor motor, Δf=1f1-F
After bringing 2l within the allowable value, the generator 1 is connected in parallel to the grid using an automatic synchronizer.

In the above embodiment, the first and second frequencies each having a desired frequency are obtained from the 1 MHz crystal oscillation circuit 109 by the frequency dividing circuit. The number of stages may be reduced, and the first frequency and second frequency may be generated independently. As described above, according to the present invention, it is possible to eliminate variations in characteristics due to variations in circuit elements in conventional devices using analog circuits, and it is easy to adjust. Automatic alignment eliminates the need for the test day (which was required on test days), and the time limit is determined accurately using a crystal oscillator and digital values, so there is no fluctuation due to parts deterioration or aging, and the set time limit can be easily changed. This provides a fast device.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional device, Figure 2 is an explanatory diagram explaining the display method of the NOR gate used in Figure 1, and Figure 3 shows the output waveforms of each full-wave rectifier in Figure 1. Figure 4 is a waveform diagram showing the voltage progression of the capacitor in Figure 1, Figure 5 is the frequency difference Δf and governor motor drive time T.
. FIG. 6 is a block diagram showing an embodiment of the present invention, FIGS. 7 and 8 are waveform diagrams showing voltage waveforms at specific parts of FIG. 6, and FIG. 10 is a correspondence diagram showing the relationship between the input and output of the ROM in FIG. 6, and FIG. 11 is a value preset to the down counter in FIG. 6. and governor motor drive time limit T. A correspondence diagram showing the relationship between Δ
It is a graph which shows the relationship between f and governor motor drive time limit. 66, 67, 68, 69... Rectangular wave generation circuit, 70... First phase difference detection circuit, 71...
. . . second phase difference detection circuit, 72 . . . third phase difference detection circuit, 76, 77 . . . first flip-flop, 78, 79 . . . th 2 flip-flop, 80, 81... third flip-flop, 105, 106... fourth flip-flop,
45...First relay, 46...Second
Relay, 102... Counter, 103...
...ROMllO4...Presettable counter, 108...Pulse interval control circuit, 10
9...Crystal oscillation circuit, 110, 111, 112
・・・・・・Frequency dividing circuit.

Claims (1)

[Claims] 1. A first phase difference for detecting a phase difference between a first phase-to-phase voltage of a three-phase AC voltage on the system side and a first phase-to-phase voltage on a generator side that generates the three-phase AC voltage. a voltage circuit, a second phase difference detection circuit that detects a phase difference between the first phase-to-phase voltage on the system side and the second phase-to-phase voltage on the generator side, and the first phase-to-phase voltage on the system side; a third phase difference detection circuit that detects a phase difference with the third phase-to-phase voltage on the generator side; a second flip-flop that is set when the output of the second phase difference detection circuit indicates a phase difference greater than or equal to the predetermined value; a third flip-flop that is set when a phase difference is indicated; a first relay operating circuit that is energized when the first flip-flop is set and then the second flip-flop is set;
The first flip-flop is set and then the third flip-flop is set.
The second flip-flop is energized when the flip-flop is set.
A relay operation circuit prohibits the third flip-flop from being set when the second flip-flop is set, and prohibits the third flip-flop from being set when the third flip-flop is set. a counter that counts the time from when the first flip-flop is set until the second or third flip-flop is set; a count value of this counter; A read-only memory that inputs and outputs a digital number that has a predetermined functional relationship with the input, a presettable down counter to which the output of this memory is preset, and a down counter that inputs a pulse of the first frequency to the down counter. A fourth flip-flop that is set by the overflow pulse when counted; a pulse interval control circuit that inputs the output of the fourth flip-flop and outputs a pulse at a time determined by the input; and this pulse interval control circuit. An automatic speed equalizing device comprising means for resetting each of the first, second, third, and fourth flip-flops by the output of. 2. Each of the first, second, and third phase difference detection circuits includes two rectangular wave generation circuits that convert two AC voltages whose mutual phase difference is to be detected into rectangular waves, and a high voltage generator of the rectangular wave voltage. Claim 1, characterized in that it is equipped with an exclusive OR gate having a logic "1" section and a logic "0" low voltage section, and each output of the two rectangular wave generating circuits as two inputs. Automatic speed equalization device as described. 3. A counter that counts the time from when the first flip-flop is set until when the second or third flip-flop is set is cleared when the first flip-flop is set. Claim 1, characterized in that a pulse of a second frequency is inputted and this input pulse is up-counted after the flip-flop is set until the second or third flip-flop is set. The automatic speed equalization device according to item 1. 4 A second frequency pulse input to a counter that counts the time from when the first flip-flop is set to when the second or third flip-flop is set, and a presettable down counter. 4. The automatic speed equalizing device according to claim 3, wherein the pulses of the first frequency to be counted down are generated from pulses of the same frequency by respective frequency dividing circuits. 5. The frequency divider circuit that generates a first frequency pulse from pulses of the same frequency and/or the frequency divider circuit that generates a second frequency pulse from the same frequency pulses includes means for changing the frequency division ratio. An automatic speed equalizing device according to claim 4, characterized in that: